Communication at millimeter wave (mmWave) frequencies is defining a new era of wireless communication. The mmWave band offers higher bandwidth communication channels versus those presently used in commercial wireless systems. The applications of mmWave are immense: wireless local and personal area networks in the unlicensed band, 5G cellular systems, not to mention vehicular area networks, ad hoc networks, and wearables. Signal processing is critical for enabling the next generation of mmWave communication. Due to the use of large antenna arrays at the transmitter and receiver, combined with radio frequency and mixed signal power constraints, new multiple-input multiple-output (MIMO) communication signal processing techniques are needed. Because of the wide bandwidths, low complexity transceiver algorithms become important. There are opportunities to exploit techniques like compressed sensing for channel estimation and beamforming. This article provides an overview of signal processing challenges in mmWave wireless systems, with an emphasis on those faced by using MIMO communication at higher carrier frequencies.

An Overview of Signal Processing Techniques for Millimeter Wave MIMO Systems

Before the emergence of ultra-wideband (UWB) radios, widely used wireless communications were based on sinusoidal carriers, and impulse technologies were employed only in specific applications (e.g. radar). In 2002, the Federal Communication Commission (FCC) allowed unlicensed operation between 3.1–10.6 GHz for UWB communication, using a wideband signal format with a low EIRP level (−41.3dBm/MHz). UWB communication systems then emerged as an alternative to narrowband systems and significant effort in this area has been invested at the regulatory, commercial, and research levels.

IEEE Transactions on Microwave Theory and Techniques and Antennas and Propagation Announce a Joint Special Issue on Ultra-Wideband (UWB) Technology

This paper presents the first reported 28-GHz phased-array IC for 5G communications. Implemented in 130-nm SiGe BiCMOS, the IC includes 32 TRX elements and features concurrent independent beams in two polarizations in either TX or RX operation. Circuit techniques to enable precise beam steering, orthogonal phase and amplitude control at each front end, and independent tapering and beam steering at the array level are presented. A TX/RX switch design is introduced which minimizes TX path loss resulting in 13.5 dBm/16 dBm Op1dB/Psat per front end with >20% peak power added efficiency of the power amplifier (including switch and off-mode LNA) while maintaining a 6 dB noise figure in the low noise amplifier (including switch and off-mode PA). Comprehensive on-wafer measurement results for the IC across multiple samples and temperature variation are presented. A package with four ICs and 64 dual-polarized antennas provides eight 16-element or two 64-element concurrent beams with 1.4°/step beam steering (<0.6° rms error) across a ±50° steering range without requiring calibration. A maximum saturated effective isotropic radiated power of 54 dBm is measured in the broadside direction for each polarization. Tapering control without requiring calibration achieves up to 20-dB sidelobe rejection without affecting the main lobe direction.

A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications

For the first time to the best of our knowledge, this paper provides an overview of millimeter-wave (mmWave) 5G antennas for cellular handsets. Practical design considerations and solutions related to the integration of mmWave phased-array antennas with beam switching capabilities are investigated in detail. To experimentally examine the proposed methodologies, two types of mesh-grid phased-array antennas featuring reconfigurable horizontal and vertical polarizations are designed, fabricated, and measured at the 60 GHz spectrum. Afterward the antennas are integrated with the rest of the 60 GHz RF and digital architecture to create integrated mmWave antenna modules and implemented within fully operating cellular handsets under plausible user scenarios. The effectiveness, current limitations, and required future research areas regarding the presented mmWave 5G antenna design technologies are studied using mmWave 5G system benchmarks.

Millimeter-Wave 5G Antennas for Smartphones: Overview and Experimental Demonstration

This paper presents a scalable 28-GHz phased-array architecture suitable for fifth-generation (5G) communication links based on four-channel ( $2\times 2$ ) transmit/receive (TRX) quad-core chips in SiGe BiCMOS with flip-chip packaging. Each channel of the quad-core beamformer chip has 4.6-dB noise figure (NF) in the receive (RX) mode and 10.5-dBm output 1-dB compression point (OP1dB) in the transmit (TX) mode with 6-bit phase control and 14-dB gain control. The phase change with gain control is only ±3°, allowing orthogonality between the variable gain amplifier and the phase shifter. The chip has high RX linearity (IP1dB = −22 dBm/channel) and consumes 130 mW in the RX mode and 200 mW in the TX mode at P1dB per channel. Advantages of the scalable all-RF beamforming architecture and circuit design techniques are discussed in detail. 4- and 32-element phased-arrays are demonstrated with detailed data link measurements using a single or eight of the four-channel TRX core chips on a low-cost printed circuit board with microstrip antennas. The 32-element array achieves an effective isotropic radiated power (EIRP) of 43 dBm at P1dB, a 45-dBm saturated EIRP, and a record-level system NF of 5.2 dB when the beamformer loss and transceiver NF are taken into account and can scan to ±50° in azimuth and ±25° in elevation with < −12-dB sidelobes and without any phase or amplitude calibration. A wireless link is demonstrated using two 32-element phased-arrays with a state-of-the-art data rate of 1.0–1.6 Gb/s in a single beam using 16-QAM waveforms over all scan angles at a link distance of 300 m.

A Low-Cost Scalable 32-Element 28-GHz Phased Array Transceiver for 5G Communication Links Based on a $2\times 2$ Beamformer Flip-Chip Unit Cell

This paper presents a W-band wafer-scale phased- array transmitter with high-efficiency on-chip antennas. The 4 × 4 array is based on an RF beamforming architecture with an equiphase distribution network and phased shifters placed on every element. The differential on-chip antennas are implemented using a 100 μm thick quartz superstrate and with a simulated efficiency of ~ 45% at 110 GHz. The phased array is designed with low mutual coupling between the elements and results in a stable active antenna impedance versus scan angle. The phased array is built in the Jazz SBC18H3 SiGe BiCMOS process, and is 6.5 × 6.0 mm2. Measurements show two-dimensional pattern scanning capabilities with a directivity of 17.0 dB, an array gain of ~26.5 dB at 110 GHz, and an EIRP of 23-25 dBm at 108-114 GHz. The power consumption is 3.4 W from a 1.9 V supply. To our knowledge, this work represents the first W-band wafer-scale phased array to-date. The application areas are in point-to-point communication systems in the 100-120 GHz range.

A 108–114 GHz 4 $\,\times\,$ 4 Wafer-Scale Phased Array Transmitter With High-Efficiency On-Chip Antennas

This paper presents a 16-element phased-array receiver for 76-84-GHz applications with built-in self-test (BIST) capabilities. The chip contains an in-phase/quadrature (I/Q) mixer suitable for automotive frequency-modulation continuous-wave radar applications, which is also used as part of the BIST system. The chip achieves 4-bit RF amplitude and phase control, an RF to IF gain of 30-35 dB at 77-84 GHz, I/Q balance of and at 76-84 GHz, and a system noise figure of 18 dB. The on-chip BIST covers the 76-84-GHz range and determines, without any calibration, the amplitude and phase of each channel, a normalized frequency response, and can measure the gain control using RF gain control. System-level considerations are discussed together with extensive results showing the effectiveness of the on-chip BIST as compared with standard S-parameter measurements.

A 76–84-GHz 16-Element Phased-Array Receiver With a Chip-Level Built-In Self-Test System

This paper presents an in-depth study of a 45-nm CMOS silicon-on-insulator (SOI) technology. Several transistor test cells are characterized and the effect of finger width, gate contact, and gate poly pitch on transistor performance is analyzed. The measured peak $f_{t}$ is 264 GHz for a 30 $\,\times\,$ 1007 nm single-gate contact relaxed-pitch transistor and the best $f_{\max}$ of 283 GHz is achieved by a 58 $\,\times\,$ 513 nm single-gate contact regular pitch transistor. The measured transistor performance agrees well with the simulations including R/C extraction up to the top metal layer. Passive components are also characterized and their performance is predicted accurately with design kit models and electromagnetic simulations. Low-noise amplifiers from $Q$ - to $W$ -band are developed in this technology and they achieve state-of-the-art noise-figure values.

45-nm CMOS SOI Technology Characterization for Millimeter-Wave Applications

An X-Band phased-array RF integrated circuit with built-in self-test (BIST) capabilities is presented. The BIST is accomplished using a miniature capacitive coupler at the input of each channel and an on-chip I/Q vector receiver. Systematic effects introduced with BIST system are covered in detail and are calibrated out of measurements. The BIST can be done at a rate of 1 MHz with 55 dB signal-to-noise-ratio and allows for the measurement of an on-chip array factor. Measurements done with BIST system agree well with S-parameter data over all test conditions. To our knowledge, this is the first implementation of an on-chip BIST with high accuracy.

A Phased Array RFIC With Built-In Self-Test Capabilities

A 16-element phased array receiver with built-in-self test (BIST) is demonstrated at 76–84 GHz. The BIST technique employs a miniature capacitive coupler located at the input port of each phased-array channel, and uses the receiver I/Q down-converter to measure the amplitude and phase of each channel. This allows for measuring the response of individual channels if one channel is turned on at a time, and an on-chip array factor if several channels are turned on and the phase between them is varied. BIST measurements done at 76–84 GHz agree very well with S-parameter measurements with a matched load and an open circuit load at each port, and show that this technique can be used to greatly lower the testing cost and improve the self-calibration of mm-wave phased-array RFICs.

Ozgur Inac

Papers

A 108–114 GHz 4 $\,\times\,$ 4 Wafer-Scale Phased Array Transmitter With High-Efficiency On-Chip Antennas

A 76–84-GHz 16-Element Phased-Array Receiver With a Chip-Level Built-In Self-Test System

45-nm CMOS SOI Technology Characterization for Millimeter-Wave Applications

A Phased Array RFIC With Built-In Self-Test Capabilities

A 76–84 GHz 16-element phased array receiver with a chip-level built-in-self-test system