P
P.A. Govindacharyulu
Researcher at Vasavi College of Engineering
Publications - 12
Citations - 98
P.A. Govindacharyulu is an academic researcher from Vasavi College of Engineering. The author has contributed to research in topics: Electron mobility & Breakdown voltage. The author has an hindex of 6, co-authored 12 publications receiving 93 citations. Previous affiliations of P.A. Govindacharyulu include Indian Institutes of Technology & Indian Institute of Science.
Papers
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Journal ArticleDOI
Large grain polycrystalline silicon from rice husk
TL;DR: In this article, rice-husk ash was used for melting and directional solidification of polycrystalline silicon ingots and the material was found to be p type with resistivity 0.1-0.3 Ω cm within the grains.
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Ionic conductivity and dielectric measurements in single crystal β-AgI
TL;DR: Ionic conductivity measurements have been made on pure, copperdoped and cadmium-doped single crystals as mentioned in this paper, and it has been shown that copper exists as Cu + in these crystals.
Journal ArticleDOI
Physics of silver halides and their applications
TL;DR: In this paper, the defect formation energies, carrier mobilities and band-structures of silver iodide have only recently been determined, and one interesting finding is the presence of high surface fields caused by differences between interstitial and vacancy formation energies which results in separation of photo-generated electron hole pairs.
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Electrical and optical properties of amorphous semiconducting GeSe and GeSbSe films
TL;DR: The electrical activation energy and optical band-gap of GeSe and GeSbSe thin films prepared by flash evaporation on to glass substrates have been determined in this paper.
Proceedings ArticleDOI
A micropower analog hearing aid on low voltage CMOS digital process
A.B. Bhattacharyya,R.S. Rana,S.K. Guha,R. Bahl,R. Anand,M.J. Zarabi,P.A. Govindacharyulu,Utkarsh Gupta,V. Mohan,J.J. Roy,A. Atri +10 more
TL;DR: A two-chip analog micropower hearing aid circuit is developed which is based on a low voltage three micron CMOS process and uses adaptive biasing of MOS Translinear Loop circuit and an innovative application of an adaptive technique in reducing the value of a degenerating linearising resistor in the input differential stage of the AGC block to enable reduction of power consumption and external component count.