The ever-increasing demands of digital computing and wireless communication have been driving the semiconductor technology to change with each passing day. Modern electronic systems integrate more complex components and devices, which results in a very complex electromagnetic (EM) field environment. EM compatibility has become one of the major issues in ICs redesign, mainly due to the lack of efficient and accurate simulation tools and expertise on noise reduction and immunity improvement. This paper reviews the state of the arts of IC, electronic package, and printed circuit board simulation and modeling technologies. It summarizes the modeling technologies for both available structures [multilayered power-ground planes and macromodeling of interconnect (INC)] and novel structures (nano-INCs and 3-D ICs based on through-silicon via technology). It also illustrates the trends of simulation and modeling technologies in EM compatibility, signal integrity, and power integrity.

Progress Review of Electromagnetic Compatibility Analysis Technologies for Packages, Printed Circuit Boards, and Novel Interconnects

The via-plate capacitance for a via transition to a multilayer printed circuit board is evaluated analytically in terms of higher order parallel-plate modes. The Green's function in a bounded coaxial cavity for a concentric magnetic ring current is first derived by introducing reflection coefficients for cylindrical waves at the inner and outer cavity walls. These walls can be perfect electric conductor (PEC)/perfect magnetic conductor(PMC) or a nonreflective perfectly matched layer. By further assuming a magnetic frill current on the via-hole in the metal plate, an analytical formula is derived for the via barrel-plate capacitance by summing the higher order modes in the bounded coaxial cavity. The convergence of the formula with the number of modes, as well as with the radius of the outer PEC/PMC wall is discussed. The analytical formula is validated by both quasi-static numerical methods and measurements. Furthermore, the formula allows the investigation of the frequency dependence of the via-plate capacitance, which is not possible with quasi-static methods.

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Analytical Evaluation of Via-Plate Capacitance for Multilayer Printed Circuit Boards and Packages

A method for modeling and analyzing vias the multilayered integrated circuits is presented. The model is based on microwave network theory. The whole via structure is divided into cascaded subnetworks, including a vertical via passing through different layers and transitions from the microstrip line and/or striplines to the vertical via. The parameters of each subnetwork are obtained from electromagnetic field analysis. Numerical results in the frequency domain and the time domain are presented. Validation of the model has been carried out by both measurements and finite-difference-time-domain (FDTD) modeling. The results show good agreement with the measurements in the frequency range for which the components of the experimental model are within specification. The time domain simulation results also agree well with the FDTD results. >

Modeling and analysis of vias in multilayered integrated circuits

MIC and MMIC packages capable of good performance at frequencies as high as 60 GHz need to have small volume, low weight, microstrip and/or coplanar waveguide (CPW) compatibility and exhibit negligible electrical interference with the rest of the circuit. In order to acquire some of these characteristics, special provisions need to be made during circuit layout and design, resulting in high-density packages. The designed circuits have a large number of interconnects which are printed on electrically small surface areas and communicate through the substrate in a direct through-via fashion or electromagnetically through appropriately etched apertures. In a circuit environment of this complexity, parasitic effects such as radiation and cross talk are intensified, thus, making the vertical interconnection problem very critical. In this paper, transitions using through-substrate vias are considered and analyzed both in the time and frequency domains using the Finite Difference Time Domain (FDTD) technique and the Finite Element Method (FEM), respectively. The merits of each method in conjunction with accuracy, computational efficiency and versatility are discussed and results are compared showing excellent agreement. Specifically, a microstrip short-circuit, a microstrip ground pad, a CPW-to-microstrip through-via transition and a channelized CPW-to-microstrip transition are analyzed and their electrical performance is studied. >

Characterization of high frequency interconnects using finite difference time domain and finite element methods

An irregular plate pair with multiple vias is analyzed by the segmentation method that divides the plate pair into a plate domain and via domains. In the via domains, all the parallel-plate modes are considered, while in the plate domain, only the propagating modes are included to account for the coupling among vias and the reflection from plate edges. Boundary conditions at both vias and plate edges are enforced and all parasitic components of via circuit are expressed analytically in terms of parallel-plate modes. The work presented in this paper indicates that a previous physics-based via circuit model from intuition is a low-frequency approximation. Analytical and numerical simulations, as well as measurements, have been used to validate the intrinsic via circuit model.

An Intrinsic Circuit Model for Multiple Vias in an Irregular Plate Pair Through Rigorous Electromagnetic Analysis

The capacitance of a simplified model of a via hole is calculated based on an integral equation approach for the surface charge density. The formulation of the problem is based on an integral equation for the surface charges combined with an analytical solution at the ground plane opening. The finite ground plane thickness is explicitly taken into account. Numerical data are obtained for a large range of realistic geometrical data. The relative importance of the contribution to the total capacitance coming from the ground plane opening is explicitly evaluated. It is found that the via capacitance is proportional to the square root of its height, at least for the range of geometrical data considered. >

Capacitance of a circular symmetric model of a via hole including finite ground plane thickness

An integral equation-based quasi-static method is described for calculating the capacitance of multilayer board via's The considered via geometry contains connecting strips, pads on the via, and a finite ground plane thickness After showing that coupling through ground plane openings is very small for realistic configurations, via's are treated as a number of independent sections (one section per multiboard layer) The influence of the geometric parameters on the via capacitance is examined; results are also compared with previous publications and with measurements >

Prediction of the excess capacitance of a via-hole through a multilayered board including the effect of connecting microstrips or striplines

A quasi-static method is described for calculating the excess inductance of via's. The considered via geometry contains connecting strips, pads on the via, and a finite ground plane thickness. An integral equation based on the scalar magnetic potential /spl psi/ is solved. The inductance is found by calculating the magnetic flux through a cut introduced to define /spl psi/ in an unequivocal way. The problem is generally solved for via through-holes; the grounded via-configuration is found as a limiting case. The influence of the geometric parameters on the via inductance is examined. >

Scalar magnetostatic potential approach to the prediction of the excess inductance of grounded via's and via's through a hole in a ground plane

Two different time-domain reflectometry (TDR)-based methods for estimating the equivalent circuit parameters of a via hole are presented. The first method is semigraphical, the second is a numerical estimation technique. Estimation is not restricted to equivalent circuit parameters, but onboard unknown rise times and delays are also included. Two possible models for a via hole are compared: a single capacitor model and a pi -network, with two capacitances and an inductance. For certain categories of via hole, the inductive component turns out to be rather important. >

Least-square estimation of the equivalent circuit parameters of a via-hole from a TDR reflectogram, including on-board rise time and delay estimation

A quasi-static method is described for calculating the excess capacitance and inductance of via's. The considered via geometry contains connecting strips, pads on the via, and finite ground plane thickness. The influence of the pad size and the size of the ground plane opening on the via capacitance, inductance and impedance is examined. >

P.A. Kok

Papers

Capacitance of a circular symmetric model of a via hole including finite ground plane thickness

Prediction of the excess capacitance of a via-hole through a multilayered board including the effect of connecting microstrips or striplines

Scalar magnetostatic potential approach to the prediction of the excess inductance of grounded via's and via's through a hole in a ground plane

Least-square estimation of the equivalent circuit parameters of a via-hole from a TDR reflectogram, including on-board rise time and delay estimation

An integral equation approach to the prediction of the capacitance and the inductance of a via through-hole