Showing papers in "IEEE Transactions on Components, Hybrids, and Manufacturing Technology in 1993"

High-speed VLSI interconnect modeling based on S-parameter measurements

Abstract: A first-level-metal single-conductor IC interconnect model is developed for high-speed and high-density VLSI circuit design. The model shows interconnect circuit parameters that vary with frequency. Existing interconnect models exclude effects such as capacitive fringing and the influence of substrate conductance. The new model represents fine-line as well as wide-line interconnect behavior over a 20-GHz frequency range and includes these effects. The model parameters are compared to scattering parameter measurements as well as numerical simulations based on PISCES-II. Excellent agreement is shown with S-parameter measurements. >

Au-In bonding below the eutectic temperature

Abstract: A bonding method using Au-In alloy which requires a low process temperature of 200 degrees C to produce high temperature (454 degrees C) bonds is reported. Multiple layers of Au and In are deposited on semiconductor wafers in one vacuum cycle to reduce In oxidation. The semiconductor dice are then bonded to substrates coated with Au. Above 157 degrees C, the indium layer melts and dissolves the Au layers to form a mixture of liquid and solid. The solid-liquid interdiffusion process continues until the mixture solidifies to form the Au-In bond. A scanning acoustic microscope (SAM) was used to determine the excellent bonding quality before and after thermal shock tests while an energy dispersive X-ray (EDX) was employed to determine the composition of the resulting bonds. The resulting bond has an unbonding temperature greater than 545 degrees C. Due to the low process temperature, the stress on the bonded structure caused by thermal expansion mismatch is reduced. This type of bonding is useful when bonding at a low temperature is followed by a subsequent higher temperature process. >

Effect of an axial magnetic field upon the development of the vacuum arc between opening electric currents (currents read contacts)

Abstract: In one series of experiments, a constant axial magnetic field B/sub ax/ was produced in the gap between opening Bruce-profile, chromium-copper contacts. Peak arc currents up to 40 kA at 50 Hz were studied with B/sub ax/ u to 112 mT. For each peak current, a critical field B/sub crit/ was determined above which anode spots did not form. For B/sub ax/ greater than B/sub crit/, the time from contact parting to the formation of a diffuse vacuum arc was linearly dependent on separation current. In a second series, the contacts were designed to generate a self B/sub ax/ when AC current up to 123 kA peak flowed. This field was approximately proportional to the current waveform through the contacts, and it was always higher than the B/sub crit/ predicted for the instantaneous current. The time from contact parting to the formation of the diffuse arc was consistent with that observed in the first experimental series. Once the diffuse arc had formed, the contacts showed no distributed melting for currents up to 81 kA, but gross melting occurred at 102-123 kA. The formation of diffuse arcs is discussed, and the anode melting is explained. >

Decoupling capacitor effects on switching noise

Abstract: The experimental procedures and test vehicles used for the characterization of the decoupling capacitor efficiency in reducing the power supply differential switching noise of the multichip-module (MCM) package structure employed in the IBM ES/9000 system are described. The experimental results are summarized for various switching elements. It is demonstrated that careful design of the test vehicles, tester systems, and probes makes the accurate measurement of Delta-1 noise feasible. Experimental results on the BOBCAT tester show that the decoupling capacitor efficiency in reducing the peak of the differential Delta-1 noise is 50-67%. This efficiency can be increased by reducing the effective inductance in the decoupling capacitor current return path. >

Processing and microwave characterization of multilevel interconnects using benzocyclobutene dielectric

Abstract: Interconnection density is one of the most significant factors affecting cost, performance, and reliability of integrated circuits (ICs) and multichip modules (MCMs). In this paper, high density multilayer interconnect structures were fabricated using gold metallization and polymer interlayer dielectric. A number of polymers were investigated and benzocyclobutene (BCB) was selected for its electrical, mechanical, and thermal properties. A design of experiments was carried out to optimize plasma etching of vias in BCB. All metal depositions were done by lift-off techniques. A microwave characterization layout was designed to evaluate microstrip transmission lines, transmission line cross-overs, and multilevel spiral inductors. Two layers of metal separated by a layer of BCB were processed on a glass wafer. RF-on-wafer measurements were carried out at frequencies from 0.1 to 20 GHz. Equivalent circuit models fitted to the experimental data were used to derive the effective dielectric constant and characteristic impedance of the transmission lines, cross-over capacitance, and inductance and Q-factor for the multilevel spiral inductors. >

Capacitance of disk capacitors

Abstract: The capacitance of a parallel-plate capacitor is formulated in basic electrostatics, assuming that the separation between the two electrode plates is very narrow and the fringe field of the edges is negligible. However, in practical problems of electrical and electronic engineering there are many cases where the plate separation is wide and the fringe field effect cannot be neglected. In the authors' previously published paper the capacitance of strip capacitor was computed by the boundary element method (BEM) for the case where the separation becomes wide, and a new empirical formula of the capacitance against the plate separation was derived. The empirical formula agreed well with experimental data. A formula for the capacitance of a parallel plate disk capacitor is presented. The formula is valid over a wider separation than formulas presented previously. As a special case of the problem, the capacitance of parallel plate ring capacitors is computed by the BEM. >

Generic reliability figures of merit design tools for surface mount solder attachments

Abstract: Adequate reliability of surface mount (SM) solder attachments can only be assured with a design for reliability (DFR) based on solder joint behavior and the underlying fatigue damage mechanisms. The perceived difficulties with a DFR stem from the very complex and only partially understood nature of the interacting mechanisms underlying thermally induced solder joint fatigue combined with the highly temperature-, time-, and stress-dependent behavior of some of the involved materials, especially solder. Generic figures of merit are presented. These figures of merit are simple design tools that can easily be utilized by nonexpert users unfamiliar with the underlying complexities of solder fatigue and give reliability assessment results in a GO/NO-GO fashion. These figures of merit not only avoid the over simplifications-originally thought necessary for simple design tools and limiting the applicability of the figures of merit-contained in Version 1 of the figures of merit, but are also simpler to apply. >

Correlation of analytical and experimental approaches to determine thermally induced PWB warpage

Abstract: Thermomechanical design effects in the printed wiring board (PWB) design process are considered, In particular, a research project for developing advanced finite-element method (FEM)-oriented capabilities to simulate thermally induced PWB warpage is reported. The FE analysis results are validated by correlating them with measurements obtained from a separate experimental approach using the shadow Moire method. >

Evaluation of a three-dimensional memory cube system

Abstract: Silicon cubes consisting of 18-20 1-Mb DRAM chips have been fabricated. In the stacking process, the chips are joined by adhesive to form the cube, interconnected by chip metallization processes, and packaged on a ceramic pin grid array (PGA) substrate that is mounted onto a memory card for testing. Modification of an existing memory card permits the substrate with cube to be substituted in place of an array of 1-Mb DRAM memory modules that normally form the card array. Memory tube operation is verified by testing both original and cube memory cards on the same memory tester. Electrical signals for each of the cards are observed and compared. Extensive electrical modeling and simulation of the cube interconnect circuitry including the chip transfer metal, interchip bus lines, and PGA substrate were performed as part of the design and later verified. A high degree of interconnect and wiring redundancy was used to guarantee connection of all the chips in the cube to the applied control signals and data lines. >

Characterization of the broadband transmission behavior of interconnections on silicon substrates

Abstract: In this paper some characteristics of the transmission behavior of interconnections on conductive silicon substrates are presented. With regard to the signal propagation in high-speed digital circuits, the broadband behavior of the lines is of special interest. The characteristic impedance Z/sub C/ and the propagation constant gamma of the lines are determined experimentally by microwave measurements. The influence of the line geometry, the substrate resistivity, and the signal frequency on the transmission behavior are clarified. Based on the results of these measurements, the suitability of the conventional RLC line model for time-domain simulations of the transmission characteristics of interconnections on silicon substrates is clarified. >

A universal nonlinear component and its application to WSI

Abstract: Presents a high-speed multifunction chip for performing one of four nonlinear operations: 1) square root, 2) reciprocal, 3) sine/cosine, and 4) arctangent. Each of these functions is evaluated with one ROM access, two additions, and one major and one minor multiplication, yielding a new result every two clock cycles. Its performance signifies an estimated three-to-four-fold increase in speed (for comparable technologies and minimum feature size) over existing approaches. Furthermore, since all four functions are performed on the same cell, a silicon-area advantage of approximately three is realized when the application demands multiple functions. In wafer scale integration (WSI) of signal and image processing algorithms, several such functions are usually needed, while defect tolerance dictates the use of just one or two types of cells. Thus the new component is ideally suited for monolithic WSI. However, it can also be used as a co-processor/accelerator for commercial DSP chips in hybrid WSI implementation of signal processing algorithms. The underlying principle, which has made the combined goals of high-speed and multifunctionality possible, is second-order interpolation of very small ROM tables. Two versions are presented: a 24-b chip, and a 16-b chip, both fabricated in 2.0- mu m CMOS technology. >

Constriction resistance of conducting spots by the boundary element method

Abstract: The finite-element method (FEM) has been applied as a powerful numerical method to the study of electric contacts. In this work, the boundary element method (BEM), is introduced into the study of contacts, and the constriction resistance of conducting spots is computed by the method. The constriction resistance of circular spot is computed, and by comparing the computed value with the exact solution presented by Holm (1979), the high accuracy of the calculated value by the BEM is assured. The constriction resistance of square spot was computed by the FEM, but the value computed by the FEM is a very rough estimation. A far more accurate value is calculated by the BEM. The conductances of ring-shaped spots against the thickness of ring are computed, and it is verified that the conductances do not decrease because of the strong current constriction at conducting spots until the thickness becomes close to zero. >

Automated vision system for inspection of IC pads and bonds

Abstract: One of the problems in increasing reliability in the manufacture of integrated circuit (IC) devices is inspection of the bond pads and the bonds connecting the bond pads to the lead fingers of the device. The continuing increase in packing density of VLSI circuits requires that the inspection process be completely automated. The authors present methods for visual inspection of bond pads and bonds, which are intended to automatically extract parameters of significance in determining their quality, from two-dimensional images taken from the top of the IC wafer. >

Relaxation effects in high-voltage barium titanate nonlinear ceramic disk capacitors

Abstract: Room-temperature capacitance-voltage-frequency measurements are reported for an 85-nF barium titanate high-voltage ceramic-disk nonlinear capacitor, intended for use in a power electronics turnoff snubber circuit. Bias-voltage excursions are from 0 to 1500 V DC, and the frequency responses are measured from quasi-DC to 1000 Hz. The observed C-V-frequency responses are modeled in terms of series-capacitance contributions from ferroelectric grains and p-n junction grain boundaries, involving 16 parameter variables. The ferroelectric capacitance terms are given by a modified Langevin function, and the grain-boundary capacitances are modeled by back-to-back p-n junction diodes on either side on an insulator boundary. The observed frequency dependence of the C-V response is attributed here to a Debye-type relaxation of the compensation regions at the grain boundaries, with time constant 15 ms. Good agreement between theory and experiment is obtained over the 0-1500-V bias range. >

A hybrid silicon carbide differential amplifier for 350 degrees C operation

Abstract: An operational amplifier has been designed, fabricated, and tested at 350 degrees C using silicon carbide MESFET pairs and thick-film hybrid technology. The amplifier was successfully tested over the temperature range of 25-350 degrees C. The gain of the amplifier was greater than 60 dB, the common-mode rejection ratio was greater than 55 dB, and the offset voltage varied from 139 to 159 mV over the entire temperature range. The results demonstrate the feasibility of high-temperature circuit design and assembly using this approach. >

Fabrication of an insulated metal substrate (IMS), having an insulating layer with a high dielectric constant

Abstract: A copper-based insulated metal substrate (IMS) having an insulating layer with a high dielectric constant has been developed, using an epoxy compound filled with barium titanate filler. A wide variety of polymers and inorganic filters as well as coupling agents were tested for their ability to be fabricated into an insulating layer having a dielectric constant of 26 and a dielectric loss of 0.04 at 400 MHz. The temperature dependence of the cured dielectric was also studied. This copper-based IMS easily allowed for the addition of solder through holes. Reduction in the size of the microstrip line in an UHF power amplifier was attempted. An area less than 1/3 the original size of the conventional glass epoxy printed circuit is expected with this IMS. >

Numerical analysis of heating transient of electric contacts under short-circuit conditions

Abstract: A model for the simulation of the heating transient of contact elements under short-circuit conditions is described. The model permits the determination of the maximum temperature reached by the contact area under defined test conditions. In such a way it is possible to identify the conditions which do not cause contact welding. Numerical results obtained by simulation have been compared to the results of an experimental investigation on normal production contacts. >

Anisotropically conductive polymer films with a uniform dispersion of particles

Abstract: Anisotropically conductive films consisting of a single layer of magnetically separated conductor spheres in a polymer matrix are described. In a vertical magnetic field, ferromagnetic spheres in a viscous medium become parallel magnetic dipoles and repel one another to produce a uniform, two-dimensional particle distribution. This structure is then frozen in by cooling or curing of the polymer matrix. In order to prevent the formation of undesirable dendritic particle protrusions, the magnetic force on the particles has to be balanced against the surface tension of the polymer and the gravity effect. As an interconnection material placed between circuit devices, the present conductive polymer films with uniformly distributed particles exhibit, as compared to the conventional, random distribution, a reduced tendency for electrical shorts and pad-to-pad variations in contact resistance values especially for fine pitch interconnections. Since the percolation stringers are no longer present in the magnetically distributed structure, it is anticipated that electric-field-induced isolation failures observed in some adhesive films will be substantially diminished. >

Shape of a nonaxisymmetric liquid solder drop constrained by parallel plates

Abstract: A differential equation describing the shape of a nonaxisymmetric solder-gas interface in cylindrical coordinates is developed using the Euler-Lagrange method. This equation is solved numerically using the method of finite differences for the geometry of a liquid drop constrained by two parallel circular plates that are separated vertically at a fixed height and displaced in the horizontal direction. For passive alignment applications, the shapes obtained can be used to calculate the restoring force produced by a drop constrained by circular plates when displaced from equilibrium. >

Modeling and simulation of coupled transmission line interconnects over a noisy reference plane

Abstract: Limitations in using conventional coupled transmission line simulators to model signal propagation over a noisy reference plane are explained. A distributed lumped element circuit model including reference plane parasitics and associated coupling (to signal conductors) parasitics is developed, and verified using SPICE simulations. Inductance and capacitance per-unit-length (pul) matrix elements are calculated using detailed two-dimensional parasitic extractors, and the partial inductance concept. Results using this model were compared with conventional "isolated" (switching noise isolated) coupled transmission line simulations. Significant differences were found. Package pin placement on the reference plane, and its impact on overall noise characteristics are analyzed. >

Future WSI technology: stacked monolithic WSI

Abstract: Describes a methodology for stacking chips vertically and interconnecting them through the chips to achieve a three-dimensional (3D) circuit. This methodology involves the integration of two technologies: indium bump interconnect technology, historically used to fabricate hybrid focal plane arrays, and the precision thinning of bonded silicon wafers by a process called Acuthin. Substantial improvements in computing density, power dissipation, and signal propagation time can be realized. This paper describes some of the techniques and benefits of this 3D interconnect methodology. >

Crosstalk analysis for high-speed pulse propagation in lossy electrical interconnections

Abstract: The effects of interconnection loss (both DC loss and skin effect loss) on crosstalk noise for a coupled lossy interconnection system, with various termination conditions, coupled lengths, spacings, and interconnection structures (microstrip lines versus strip lines) are investigated. Fourier transform techniques and numerical methods are applied to solve the coupled transmission line equations for the strong coupling case (mutual coupling between the active line and the quiet line). The interconnection is either terminated by its approximated matched load impedance, R/sub o/, or by the equivalent loading capacitance of the receiver, C/sub L/. General design guidelines for controlling the crosstalk noise and reflection noise in lossy interconnections are discussed. >

200 degrees C operation of semiconductor power devices

Abstract: There is a growing need for commercial and military power electronics to operate above 175 degrees C. Changes in operating parameters at 200 degrees C have been measured for four devices, an NPN bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), an N-channel metal-oxide-semiconductor field effect transistor (MOSFET), and a P-type MOS controlled thyristor (MCT). Using the results of these measurements, power supplies have been built using IGBTs and MOSFETs and operated at an ambient temperature of 200 degrees C for up to 72 h. >

New densification process of thick films

Abstract: Standard inks for low-cost screen-printed components generally contain a glass binder for adhesion and filling. However, for applications where the original properties of the active material must not be changed, a glass-free ink is highly desirable. To ensure a good densification of screen-printed films without inorganic binder, it is proposed that the application of a mechanical pressure be added to the standard process. This new process has been used to fabricate low-voltage single-in-line varistors, capacitors, and pyroelectric components with sandwich electrodes. Such a configuration is difficult to obtain when, as in the standard screen-printing procedure, no pressure is applied to the films. Conductors, resistors, and semiconductor chemical sensors prepared with this technology have also been investigated. >

Large capacitance electric double layer capacitor using activated carbon/carbon composite

Abstract: An electric double-layer capacitor with large capacitance, 1000 F at 5.5 V, has been developed. It uses activated carbon/carbon (AC/C) composite as the polarizable electrodes and sulfuric acid as the electrolyte. The AC/C composite was synthesized through a simple process, namely, a cured mixture of activated carbon and phenol-formaldehyde resin was carbonized. The AC/C composite has a large surface area, 1300 mg, and low resistivity, 0.01 Omega -cm. Two kinds of pores exist in the AC/C composite: macropores with submicrometer diameters, and micropores with below 4-nm diameter. The micropores are impregnated with the sulfuric acid aqueous solution through the macropores open to the outer surface. The electric double-layer capacitance per unit volume for the AC/C composite in sulfuric acid is greater than that for activated carbon powder as a raw material. The capacitor is expected to be used as an energy storage device and a supplementary power source. >

Formation of SiO/sub 2/ on contact surface and its effect on contact reliability

Abstract: Electrical contact failure due to thermal decomposition of low-molecular-weight silicone vapor evaporated from such silicone products as oils and rubbers was investigated in a simulated environment. A glassy film deposit was found on the contact surface after exposure to elevated temperature in an atmosphere containing an extremely small quantity of the silicone. The film was clearly identified as amorphous SiO/sub 2/ by ellipsometry, X-ray photoelectron spectrometry (XPS), and X-ray diffractometry (XRD). The growth of the film was directly related to the concentration of silicone vapor and temperature. The growth law was an exponential function of the exposure time. The film increases static contact resistance when it is thicker than 800 AA and the load is less than 5 g. The relationship between the concentration of the vapor, temperature, film thickness, and contact resistance is represented schematically. >

A wafer scale visual-to-thermal converter

Abstract: Wafer scale transducer arrays (WSTA's) containing multitransducer arrays combined with processing circuits are produced using a combination of CMOS technology, silicon micromachining, and laser interconnection techniques. A prototype wafer scale visual-to-thermal converter is being developed to convert a visual scene to thermal scene with the same resolution. The basic array is composed of transducer pixels, which combine photodetectors and thermal emitters as transducers together with signal conditioning and control circuitry, enabling 75%-50% local redundancy of system components. Unlike digital WSI designs, the WSTA redundancy approach is driven by regularity in transducer location and emphasizes local over global transducer sparing even when considering cluster defects. For WSTA, testing of functioning cells for WSI must be supplemented by compensating the transducer nonuniformities across the array. >

Finite-difference time-domain analysis of pulse propagation in multichip module interconnects

Abstract: The application of the finite-difference-time-domain (FDTD) method to the electromagnetic characterization of multichip-module (MCM) interconnects with perforated (mesh) reference planes is demonstrated. The limitations of the method in finding transmission line propagation characteristics (i.e., characteristic impedance Z/sub 0/ and phase constant beta ) are investigated. An alternative approach for the characterization of MCM interconnects which exploits the capabilities of the FDTD method is suggested. This alternative approach uses the results from the FDTD method to extract the per unit length delay and approximate impulse response of the system. These results can be used to identify the effects of the perforated reference plane on signal propagation. The validity of the TEM approximation for signal propagation in realistic MCM structures is also examined. >

Statistics of solder joint alignment for optoelectronic components

Abstract: The use of an area array of solder joints allows the self-alignment of a large number of components in microelectronic packages. The sensitivity to statistical variations in solder joint volumes is investigated. The analysis shows that sufficiently large arrays of randomly distributed volumes lead to very narrow distributions in the height and tilt of one component relative to another. >

A new de-embedding technique for on-board structures applied to the bandwidth measurement of packages

Abstract: A de-embedding technique for on board structures or devices under tests (DUTs) is presented. The key feature of the method is the comparison between the S-parameter data for the embedded DUT and the data for a judiciously chosen reference situation. The technique also uses the time-domain option of modern network analyzers. The approach is illustrated by detailed bandwidth measurements for a high pin count package. >