http://eia.udg.es/%7Eqsalvi/papers/2006-MJ.pdf

Review of CMOS image sensors

Metal silicides have played an indispensable role in the rapid developments of microelectronics since PtSi was first used to improve the rectifying characteristics of diodes in early 1960s. This wo ...

Metal silicides in CMOS technology : Past, present, and future trends

CMOS based imagers are beginning to compete against CCDs in many areas of the consumer market because of their system-on-a-chip capability. Sensitivity, however, is a main weakness of CMOS imagers and enhancements and deviations from standard CMOS processes are necessary to keep up sensitivity with downscaled process generations. In the introductory section several definitions for the sensitivity of image sensors are reviewed with regard to their potential to allow meaningful comparison of different detector structures. In the main section, the standard CMOS sensor architecture is compared to detector structures designed to improve the sensitivity, namely the photogate (PG), the pinned photodiode (PPD) and the thin film on ASIC (TFA) approach. The latter uses a vertical integration of the photodiode on top of the pixel transistors. A careful analysis of the relevant electrical, optical and technological parameters and many previously published experimental data for different imagers reveals that only the PPD and the TFA enhancements provide satisfactory sensitivity and withstand scaling down to 0.18 /spl mu/ processes. Due to the higher fill factor and the higher quantum efficiency TFA provides significantly better values than PPD. The radiometric sensitivity of a 5 /spl mu/m/spl times/5 /spl mu/m TFA pixel is found to amount to 11.9 V/(/spl mu//cm/sup 2/) for a 0.25 /spl mu/m process and 27.5 V/(/spl mu/J/cm/sup 2/) for a 0.18 /spl mu/m process.

Sensitivity of CMOS based imagers and scaling perspectives

This paper introduces a new hyperchaotic system by adding an additional state into the third-order Liu chaotic system. Some of its basic dynamical properties, such as the hyperchaotic attractor, Lyapunov exponent, fractal dimension and the hyperchaotic attractor evolving into chaotic, periodic, quasi-periodic dynamical behaviours by varying parameter d are studied briefly. Various attractors are illustrated not only by computer simulation but also by conducting an electronic circuit experiment.

Hyperchaos evolved from the Liu chaotic system

A storage pixel sensor disposed on a semiconductor substrate comprises a photosensor. At least one nonlinear capacitive element is coupled to the photosensor. At least one nonlinear capacitive element is arranged to have a compressive photocharge-to-voltage gain function. An amplifier has an input coupled to the nonlinear capacitor and an output. Other, non-capacitive elements may be employed to produce a compressive photo-charge-to-voltage gain having at least one breakpoint.

Storage pixel sensor and array with compression

This paper reports the experimental results of the first CMOS active pixel image sensors (APS) fabricated using a high-performance 1.8-V, 0.25-/spl mu/m CMOS logic technology. No process modifications were made to the CMOS logic technology so that the impact of device scaling on the image sensing performance can be studied. This paper highlights the device and process design considerations required to enable CMOS as an image sensor technology.

CMOS active pixel image sensors fabricated using a 1.8-V, 0.25-/spl mu/m CMOS technology

An experiment to determine the effect of gate electrode resistivity on circuit speed gave unexpected results: circuits with the lowest sheet resistance had the poorest circuit speed. Explanation of this behaviour required development of a new high-frequency method of measuring the impedance of the gate electrode. This method revealed that the circuits with a composite gate electrode had been formed with a partial discontinuity. The measurement technique is described, and the evidence of the discontinuity is shown. The effect of the discontinuity on device and circuit speed is demonstrated.

Identification of gate electrode discontinuities in submicron CMOS technologies, and effect on circuit performance

The importance of vertical continuity of the gate electrodes of submicron CMOS circuits is discussed A high frequency technique for assessing this continuity is demonstrated An example of a gate structure with poor vertical continuity is shown, and the effect on circuit operation is presented >

P.D. Agnello

Papers

CMOS active pixel image sensors fabricated using a 1.8-V, 0.25-/spl mu/m CMOS technology

Identification of gate electrode discontinuities in submicron CMOS technologies, and effect on circuit performance

Submicron CMOS gate electrode discontinuity: electrical signature and effect on circuit speed