Proceedings ArticleDOI
Implementation of adder structure with fast carry network for high speed processor
Anand N,George Joseph,Johny S. Raj,P. Jayakrishnan +3 more
- pp 188-190
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TLDR
This paper discusses about the implementation of Carry Select Adder combining with the possibilities of Kogge Stone Adder, which shows the adder gives better performance in terms of speed and area implementation.Abstract:
High performance digital adder with reduced area and low power consumption is an important design constraint for advanced processors The speed of operation of such an adder is limited by carry propagation from input to output Our work is based on designing an optimized adder for advanced processors This paper discusses about the implementation of Carry Select Adder combining with the possibilities of Kogge Stone Adder Kogge Stone parallel approach will give option to generate fast carry for intermediate stages The adder is implemented on Xilinx Virtex 5 FPGA devices and is compared with RCA adder and Kogge Stone adder Result shows the adder gives better performance in terms of speed and area implementationread more
Citations
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Proceedings ArticleDOI
High Speed Power Efficient Carry Select Adder Design
TL;DR: A new CSA architecture using Manchester carry chain in multioutput domino CMOS logic employs a novel MCC blocks in an hierarchical approach in the design of the CSA to achieve two fold advantages in terms of power-delay product (PDP) and hardware overhead.
Proceedings ArticleDOI
Kogge Stone Adder with GDI technique in 130nm technology for high performance DSP applications
TL;DR: A 64 bit GDI logic based KSA schematic is designed by using Mentor Graphics EDA Tool in 130nm Technology and the best adder in terms of performance is observed as the one with a delay of 407.07ps designed in GDI Technique.
Proceedings ArticleDOI
Implementation of efficient portable low delay adder using FPGA
TL;DR: The goal of this paper is to efficiently carry out the proposed CSHA adder with carry increment circuit over FPGA kit and the performance of this proposed adder circuit is better than other related ones in both area and delay.
References
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Journal ArticleDOI
A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations
Peter M. Kogge,Harold S. Stone +1 more
TL;DR: This paper uses a technique called recursive doubling in an algorithm for solving a large class of recurrence problems on parallel computers such as the Iliac IV.
Journal ArticleDOI
High-Speed Arithmetic in Binary Computers
TL;DR: Methods of obtaining high speed in addition, multiplication, and division in parallel binary computers are described and then compared with each other as to efficiency of operation and cost.
Journal ArticleDOI
Conditional-Sum Addition Logic
TL;DR: A comparison of several adders shows that, within a set of stated assumptions, conditional-sum addition is superior in certain respects, including processing speed.
Journal ArticleDOI
Carry-Select Adder
TL;DR: The adder system described increases the speed of the addition process by reducing the carry-propagation time to the minimum commensurate with economical circuit design.
Journal ArticleDOI
Low-Power and Area-Efficient Carry Select Adder
B. Ramkumar,Harish M. Kittur +1 more
TL;DR: This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA, and develops and compared with the regular SQRT C SLA architecture.