The need for ultra low-power, area efficient, and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. In this paper, an analysis on the delay of the dynamic comparators will be presented and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore the tradeoffs in dynamic comparator design. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double-tail comparator is modified for low-power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, which results in remarkably reduced delay time. Post-layout simulation results in a 0.18- μm CMOS technology confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator can be increased to 2.5 and 1.1 GHz at supply voltages of 1.2 and 0.6 V, while consuming 1.4 mW and 153 μW, respectively. The standard deviation of the input-referred offset is 7.8 mV at 1.2 V supply.

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Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator

To advance our understanding of the functioning of neuronal ensembles, systems are needed to enable simultaneous recording from a large number of individual neurons at high spatiotemporal resolution and good signal-to-noise ratio. Moreover, stimulation capability is highly desirable for investigating, for example, plasticity and learning processes. Here, we present a microelectrode array (MEA) system on a single CMOS die for in vitro recording and stimulation. The system incorporates 26,400 platinum electrodes, fabricated by in-house post-processing, over a large sensing area (3.85 × 2.10 mm2) with sub-cellular spatial resolution (pitch of 17.5 μm). Owing to an area and power efficient implementation, we were able to integrate 1024 readout channels on chip to record extracellular signals from a user-specified selection of electrodes. These channels feature noise values of 2.4 μVrms in the action-potential band (300 Hz-10 kHz) and 5.4 μVrms in the local-field-potential band (1 Hz-300 Hz), and provide programmable gain (up to 78 dB) to accommodate various biological preparations. Amplified and filtered signals are digitized by 10 bit parallel single-slope ADCs at 20 kSamples/s. The system also includes 32 stimulation units, which can elicit neural spikes through either current or voltage pulses. The chip consumes only 75 mW in total, which obviates the need of active cooling even for sensitive cell cultures.

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A 1024-Channel CMOS Microelectrode Array With 26,400 Electrodes for Recording and Stimulation of Electrogenic Cells In Vitro

A high-performance CMOS image sensor (CIS) with 13-b column-parallel single-ended cyclic ADCs is presented The simplified single-ended circuits for the cyclic ADC are squeezed into a 56-mum-pitch single-side column The proposed internal reference generation and return-to-zero digital signal feedback techniques enhance the ADC to have low read noise, a high resolution of 13 b, and a resulting dynamic range of 71 dB An ultralow vertical fixed pattern noise of 01 erms - is attained by a digital CDS technique, which performs A/D conversion twice in a horizontal scan period (6 mus) The implemented CIS with 018-mum technology operates at 390 frames/s and has 707-V/lx middots sensitivity, 61- muV/e- conversion gain, 49-erms - read noise, and less than 04 LSB differential nonlinearity

A High-Speed Low-Noise CMOS Image Sensor With 13-b Column-Parallel Single-Ended Cyclic ADCs

This paper presents a 9-bit subrange analog-to-digital converter (ADC) consisting of a 3.5-bit flash coarse ADC, a 6-bit successive-approximation-register (SAR) fine ADC, and a differential segmented capacitive digital-to-analog converter (DAC). The flash ADC controls the thermometer coarse capacitors of the DAC and the SAR ADC controls the binary fine ones. Both theoretical analysis and behavioral simulations show that the differential non-linearity (DNL) of a SAR ADC with a segmented DAC is better than that of a binary ADC. The merged switching of the coarse capacitors significantly enhances overall operation speed. At 150 MS/s, the ADC consumes 1.53 mW from a 1.2-V supply. The effective number of bits (ENOB) is 8.69 bits and the effective resolution bandwidth (ERBW) is 100 MHz. With a 1.3-V supply voltage, the sampling rate is 200 MS/s with 2.2-mW power consumption. The ENOB is 8.66 bits and the ERBW is 100 MHz. The FOMs at 1.3 V and 200 MS/s, 1.2 V and 150 MS/s and 1 V and 100 MS/s are 27.2, 24.7, and 17.7 fJ/conversion-step, respectively.

A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS

A novel dynamic latched comparator with offset voltage compensation is presented. The proposed comparator uses one phase clock signal for its operation and can drive a larger capacitive load with complementary version of the regenerative output latch stage. As it provides a larger voltage gain up to 22 V/V to the regenerative latch, the input-referred offset voltage of the latch is reduced and metastability is improved. The proposed comparator is designed using 90 nm PTM technology and 1 V power supply voltage. It demonstrates up to 24.6% less offset voltage and 30.0% less sensitivity of delay to decreasing input voltage difference (17 ps/decade) than the conventional double-tail latched comparator at approximately the same area and power consumption. In addition, with a digitally controlled capacitive offset calibration technique, the offset voltage of the proposed comparator is further reduced from 6.03 to 1.10 mV at 1-sigma at the operating clock frequency of 3 GHz, and it consumes 54 μW/GHz after calibration.

A novel low-power, low-offset, and high-speed CMOS dynamic latched comparator

The latched comparator is a building block of virtually all analog-to-digital converter architectures. It uses a positive feedback mechanism to regenerate the analog input signal into a full-scale digital level. The large voltage variations in the internal nodes are coupled to the input, disturbing the input voltage-this is usually called kickback noise. This brief reviews existing solutions to minimize the kickback noise and proposes two new ones. HSPICE simulations of comparators implemented in a 0.18-/spl mu/m technology demonstrate their effectiveness.

Kickback noise reduction techniques for CMOS latched comparators

The latched comparator is utilized in virtually all analog-to-digital converter architectures. It uses a positive feedback mechanism to regenerate the analog input signal into a full-scale digital level. Such high voltage variations in the regeneration nodes are coupled to the input voltage - kickback noise. This paper reviews existing solutions to minimize the kickback noise and proposes two new ones. HSPICE simulations verify the effectiveness of our techniques.

Low kickback noise techniques for CMOS latched comparators

Metastability is the inability of a latched comparator to reach a decision in the available amount of time. Existing analyses of metastability disregard noise, treating it as a deterministic phenomenon that inevitably happens every-time the input voltage, vIdiff, falls in a certain interval around 0, and which is restricted to the aforementioned interval. Also, according to the conventional analysis, the decision takes an infinite amount of time if vIdiff = 0 . This work analyzes metastability in the presence of noise, showing it is actually a random phenomenon whose probability of occurrence is derived. It is concluded that there is no input value for which metastability inevitably occurs (not even vIdiff = 0), and that there may be a significant probability of metastability at input voltage values much larger than those predicted by conventional analysis. All the theoretical results are in agreement with extensive HSPICE transient noise simulations.

Comparator Metastability in the Presence of Noise

The averaging technique is used in flash analog-to-digital converters to reduce nonlinearities resulting from random offset voltages of the pre-amplifiers, which stand before the comparators. The main contribution of this paper is to provide further insight into this technique, through exact closed-form expressions obtained for the output voltage, gain, integral nonlinearity and differential nonlinearity in averaged pre-amplifiers. These theoretical results are compared with HSPICE simulations, and a very good agreement is found. Finally an automatic design procedure is described, which is based on the expressions derived, and a design example is given.

Averaging technique in flash analog-to-digital converters

It is well known that low noise amplification can be performed by using a capacitor whose capacitance can be controlled. In this paper, it is shown that changing the inversion level of a MOS transistor allows voltage amplification. The theoretical characterization of this amplifier in terms of gain and harmonic distortion is made, and comparisons with HSPICE results are performed. Finally, some practical considerations to improve the performance of the circuit are presented.

P.M. Figueiredo

Papers

Kickback noise reduction techniques for CMOS latched comparators

Low kickback noise techniques for CMOS latched comparators

Comparator Metastability in the Presence of Noise

Averaging technique in flash analog-to-digital converters

The MOS capacitor amplifier