There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-/spl mu/m CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 /spl mu/Vrms and a power dissipation of 80 /spl mu/W while consuming 0.16 mm/sup 2/ of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 /spl mu/W while maintaining a similar noise-power tradeoff.

A low-power low-noise CMOS amplifier for neural recording applications

A CMOS low-power low-noise monolithic instrumentation amplifier (IA) is described. The power drain is reduced by use of current feedback and by use of only single-stage operational transconductance amplifiers in the low-frequency loop. The bandwidth of the IA is designed for medical purposes (0.5-500 Hz) and it can produce variable gains of 14/20/26/40 dB, which are set by control software.

A micropower low-noise monolithic instrumentation amplifier for medical purposes

There is a need among scientists and clinicians for low-noise, low-power biosignal amplifiers capable of amplifying signals in the mHz to kHz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully-implantable multielectrode arrays has created the need for fully-integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudo-resistor to amplify signals down to the mHz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches that limit. The resulting amplifier, built in a standard 1.5/spl mu/m CMOS process, passes signals from 0.1mHz to 7.2kHz with an input-referred noise of 2.2/spl mu/Vrms and a power dissipation of 80/spl mu/W while consuming 0.16mm/sup 2/ of chip area.

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A low-power, low-noise CMOS amplifier for neural recording applications

There is a growing demand for low-power, small-size and ambulatory biopotential acquisition systems. A crucial and important block of this acquisition system is the analog readout front-end. We have implemented a low-power and low-noise readout front-end with configurable characteristics for Electroencephalogram (EEG), Electrocardiogram (ECG), and Electromyogram (EMG) signals. Key to its performance is the new AC-coupled chopped instrumentation amplifier (ACCIA), which uses a low power current feedback instrumentation amplifier (IA). Thus, while chopping filters the 1/f noise of CMOS transistors and increases the CMRR, AC coupling is capable of rejecting differential electrode offset (DEO) up to plusmn50 mV from conventional Ag/AgCl electrodes. The ACCIA achieves 120 dB CMRR and 57 nV/radicHz input-referred voltage noise density, while consuming 11.1 muA from a 3 V supply. The chopping spike filter (CSF) stage filters the chopping spikes generated by the input chopper of ACCIA and the digitally controllable variable gain stage is used to set the gain and the bandwidth of the front-end. The front-end is implemented in a 0.5 mum CMOS process. Total current consumption is 20 muA from 3V

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A 60 $\mu$ W 60 nV/ $\surd$ Hz Readout Front-End for Portable Biopotential Acquisition Systems

The design and implementation of a fully integrated complementary metal-oxide-semiconductor (CMOS) sixth-order 2.4 Hz low-pass fitter (LPF) for medical applications is presented. For the implementation of large-time constants both linearized operational transconductance amplifiers with reduced transconductance and impedance scalers schemes for grounded capacitors are employed. Experimental results for the filter have shown a dynamic range (DR) of 60 dB, while the harmonic distortion components are below -50 dB. The power consumption for the filter is below 10 /spl mu/W, the power supply is /spl plusmn/1.5 V, and the active area is 1 mm/sup 2/. The filter was fabricated in a double poly double metal 0.8 /spl mu/m CMOS process.

/pdf/a-60-db-dynamic-range-cmos-sixth-order-2-4-hz-low-pass-4yb5at7oe7.pdf

A 60-dB dynamic-range CMOS sixth-order 2.4-Hz low-pass filter for medical applications

A switched-capacitor integrator circuit with very high time constant using capacitive T-cells, is presented. According to a set of design equations and constraints, a test circuit previously needing an excessive capacitive ratio of over 700 has been integrated with a capacitance spread of only 25. Contrary to other designs, a simple clocking scheme is sufficient. Calculations and measurements show that in the T-cell integrator, capacitive area is conveniently traded off against amplifier specifications as open-loop and slew rate; power consumption is not necessarily compromised by these specifications. Integration of an experimental test circuit has given evidence of the ease of implementing this technique in larger systems.

An area-efficient approach to the design of very-large time constants in switched-capacitor integrators

A switched-capacitor instrumentation amplifier which uses correlated-double sampling to reduce the amplifier offset is discussed. Additional offset caused by clock-related charge injection is cancelled by a symmetrical differential circuit topology and a three-phase clocking scheme. An experimental low-power test cell has been integrated, showing 100 /spl mu/V equivalent offset voltage and input noise equal to 270 /spl mu/V. For a fixed gain equal to 10- and 9-kHz sampling frequency, the power dissipation is 36 /spl mu/W (power supply: 5 V); the circuit measures only 0.2 mm/SUP 2/.

/pdf/micropower-high-performance-sc-building-block-for-integrated-3zrygxab03.pdf

Micropower high-performance SC building block for integrated low-level signal processing

A circuit technique to simulate large variable capacitance of both positive and negative polarities over a given frequency range is discussed The simulated capacitance can be varied by voltage control from -60 to +100 pF The capacitor-simulating circuit is connected in parallel with a resonator to tune its parallel resonance An oscillator with grounded resonator is also developed Together with the variable capacitor, a voltage-controlled crystal oscillator (VCXO) is realized The oscillation frequency of the oscillator can be tuned continuously from 452 to 461 kHz by voltage control Detailed analyses to completely characterize the oscillator with a simple expression are presented The prototype of the VCXO has been fabricated in a 4- mu m standard CMOS process >

Design and implementation of a CMOS VCXO for FM stereo decoders

Very large pole/sampling-frequency ratios in SC filters require large capacitance ratios and thus result in inefficient area consumption. The use of a T-cell capacitance network allows one to integrate a very large time constant (VLT) integrator, which is, to the first order, insensitive to op-amp offset.

T-cell SC integrator synthesises very large capacitance ratios

One of the major problems in biomedical and other signal processing circuit designs is the reduction of power consumption. If the amplifiers of a switched-capacitor (SC) filter are coupled together in one of the clock phases, then they have much higher gain-bandwidth requirements than in an uncoupled configuration. This results in a more than proportional increase in power consumption. Two formalism will be discussed here, which lead to analytical derivations of minimal amplifier requirements. In the first concept, one of the amplifiers in the circuit is isolated. Formulas are derived for the loop gain around that amplifier, as the form of the loop gain T(s) determines total charge transfer inaccuracy errors. The other one comments the matrix representation presented by [6]. Here, it is shown that coupling integrating amplifiers in a loop, leads to very inefficient use of the bandwidth of the amplifiers, and hence to excess power consumption.

P.M. Van Peteghem

Papers

An area-efficient approach to the design of very-large time constants in switched-capacitor integrators

Micropower high-performance SC building block for integrated low-level signal processing

Design and implementation of a CMOS VCXO for FM stereo decoders

T-cell SC integrator synthesises very large capacitance ratios

Power consumption versus filter topology in SC filters