Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given, and upset mechanisms in dynamic random access memories, static random access memories, and combinational logic are detailed. Techniques for mitigating single-event upset are described, as well as methods for predicting device and circuit single-event response using computer simulations. The impact of technology trends on single-event susceptibility and future areas of concern are explored.

Basic mechanisms and modeling of single-event upset in digital microelectronics

Part I: Background and Fundamentals Introduction, Mohamed Gad-el-Hak, University of Notre Dame Scaling of Micromechanical Devices, William Trimmer, Standard MEMS, Inc., and Robert H. Stroud, Aerospace Corporation Mechanical Properties of MEMS Materials, William N. Sharpe, Jr., Johns Hopkins University Flow Physics, Mohamed Gad-el-Hak, University of Notre Dame Integrated Simulation for MEMS: Coupling Flow-Structure-Thermal-Electrical Domains, Robert M. Kirby and George Em Karniadakis, Brown University, and Oleg Mikulchenko and Kartikeya Mayaram, Oregon State University Liquid Flows in Microchannels, Kendra V. Sharp and Ronald J. Adrian, University of Illinois at Urbana-Champaign, Juan G. Santiago and Joshua I. Molho, Stanford University Burnett Simulations of Flows in Microdevices, Ramesh K. Agarwal and Keon-Young Yun, Wichita State University Molecular-Based Microfluidic Simulation Models, Ali Beskok, Texas A&M University Lubrication in MEMS, Kenneth S. Breuer, Brown University Physics of Thin Liquid Films, Alexander Oron, Technion, Israel Bubble/Drop Transport in Microchannels, Hsueh-Chia Chang, University of Notre Dame Fundamentals of Control Theory, Bill Goodwine, University of Notre Dame Model-Based Flow Control for Distributed Architectures, Thomas R. Bewley, University of California, San Diego Soft Computing in Control, Mihir Sen and Bill Goodwine, University of Notre Dame Part II: Design and Fabrication Materials for Microelectromechanical Systems Christian A. Zorman and Mehran Mehregany, Case Western Reserve University MEMS Fabrication, Marc J. Madou, Nanogen, Inc. LIGA and Other Replication Techniques, Marc J. Madou, Nanogen, Inc. X-Ray-Based Fabrication, Todd Christenson, Sandia National Laboratories Electrochemical Fabrication (EFAB), Adam L. Cohen, MEMGen Corporation Fabrication and Characterization of Single-Crystal Silicon Carbide MEMS, Robert S. Okojie, NASA Glenn Research Center Deep Reactive Ion Etching for Bulk Micromachining of Silicon Carbide, Glenn M. Beheim, NASA Glenn Research Center Microfabricated Chemical Sensors for Aerospace Applications, Gary W. Hunter, NASA Glenn Research Center, Chung-Chiun Liu, Case Western Reserve University, and Darby B. Makel, Makel Engineering, Inc. Packaging of Harsh-Environment MEMS Devices, Liang-Yu Chen and Jih-Fen Lei, NASA Glenn Research Center Part III: Applications of MEMS Inertial Sensors, Paul L. Bergstrom, Michigan Technological University, and Gary G. Li, OMM, Inc. Micromachined Pressure Sensors, Jae-Sung Park, Chester Wilson, and Yogesh B. Gianchandani, University of Wisconsin-Madison Sensors and Actuators for Turbulent Flows. Lennart Loefdahl, Chalmers University of Technology, and Mohamed Gad-el-Hak, University of Notre Dame Surface-Micromachined Mechanisms, Andrew D. Oliver and David W. Plummer, Sandia National Laboratories Microrobotics Thorbjoern Ebefors and Goeran Stemme, Royal Institute of Technology, Sweden Microscale Vacuum Pumps, E. Phillip Muntz, University of Southern California, and Stephen E. Vargo, SiWave, Inc. Microdroplet Generators. Fan-Gang Tseng, National Tsing Hua University, Taiwan Micro Heat Pipes and Micro Heat Spreaders, G. P. "Bud" Peterson, Rensselaer Polytechnic Institute Microchannel Heat Sinks, Yitshak Zohar, Hong Kong University of Science and Technology Flow Control, Mohamed Gad-el-Hak, University of Notre Dame) Part IV: The Future Reactive Control for Skin-Friction Reduction, Haecheon Choi, Seoul National University Towards MEMS Autonomous Control of Free-Shear Flows, Ahmed Naguib, Michigan State University Fabrication Technologies for Nanoelectromechanical Systems, Gary H. Bernstein, Holly V. Goodson, and Gregory L. Snider, University of Notre Dame Index

The MEMS Handbook

Silicon integrated circuit spiral inductors and transformers are analyzed using electromagnetic analysis. With appropriate approximations, the calculations are reduced to electrostatic and magnetostatic calculations. The important effects of substrate loss are included in the analysis. Classic circuit analysis and network analysis techniques are used to derive two-port parameters from the circuits. From two-port measurements, low-order, frequency-independent lumped circuits are used to model the physical behavior over a broad-frequency range. The analysis is applied to traditional square and polygon inductors and transformer structures as well as to multilayer metal structures and coupled inductors. A custom computer-aided-design tool called ASITIC is described, which is used for the analysis, design, and optimization of these structures. Measurements taken over a frequency range from 100 MHz to 5 GHz show good agreement with theory.

/pdf/analysis-design-and-optimization-of-spiral-inductors-and-2lhr7rsegu.pdf

Analysis, design, and optimization of spiral inductors and transformers for Si RF ICs

With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. In this paper, we present a review of the power estimation techniques that have recently been proposed. >

A survey of power estimation techniques in VLSI circuits

Twenty-first century opportunities for GSI will be governed in part by a hierarchy of physical limits on interconnects whose levels are codified as fundamental, material, device, circuit, and system. Fundamental limits are derived from the basic axioms of electromagnetic, communication, and thermodynamic theories, which immutably restrict interconnect performance, energy dissipation, and noise reduction. At the material level, the conductor resistivity increases substantially in sub-50-nm technology due to scattering mechanisms that are controlled by quantum mechanical phenomena and structural/morphological effects. At the device and circuit level, interconnect scaling significantly increases interconnect crosstalk and latency. Reverse scaling of global interconnects causes inductance to influence on-chip interconnect transients such that even with ideal return paths, mutual inductance increases crosstalk by up to 60% over that predicted by conventional RC models. At the system level, the number of metal levels explodes for highly connected 2-D logic megacells that double in size every two years such that by 2014 the number is significantly larger than ITRS projections. This result emphasizes that changes in design, technology, and architecture are needed to cope with the onslaught of wiring demands. One potential solution is 3-D integration of transistors, which is expected to significantly improve interconnect performance. Increasing the number of active layers, including the use of separate layers for repeaters, and optimizing the wiring network, yields an improvement in interconnect performance of up to 145% at the 50-nm node.

/pdf/interconnect-limits-on-gigascale-integration-gsi-in-the-21st-4iloxnfjg6.pdf

Interconnect limits on gigascale integration (GSI) in the 21st century

The authors investigate a power estimation technique for VLSI that combines the accuracy of simulation-based techniques with the speed of the probabilistic techniques. The resulting method is statistical in nature; it consists of applying randomly generated input patterns to the circuit and monitoring, with a simulator, the resulting power value. This is continued until a value of power is obtained with a desired accuracy, at a specified confidence level. The authors present the algorithm and experimental results, and discuss the superiority of the approach. >

A Monte Carlo approach for power estimation

An empirical model for multilevel interconnect capacitance is presented. This is the first model that allows designers to compute capacitances of arbitrary complex metal geometries. Such flexibility is achieved by a novel strategy of constructing complex geometries from simple primitive cells. Agreement with accurate simulations and measurements is within 8% over an extensive range of dimensions. >

Multilevel metal capacitance models for CAD design synthesis systems

A current-estimation approach to support the analysis of electromigration (EM) failures in power supply and ground buses of CMOS VLSI circuits is discussed. It uses the original concept of probabilistic simulation to efficiently generate accurate estimates of the expected current waveform required for electromigration analysis. Thus, the approach is pattern-independent and relieves the designer of the tedious task of specifying logical input waveforms. This approach has been implemented in the program CREST (current estimator) which has shown excellent accuracy and dramatic speedups compared with traditional approaches. The approach and its implementation are described, and the results of numerous CREST runs on real circuits are presented. >

Probabilistic simulation for reliability analysis of CMOS VLSI circuits

A new semiconductor controlled rectifier which may be used to provide on-chip protection against ESD stress applied at the input, output, power supply pins or between any arbitrary pair of pins of an integrated circuit is disclosed. The structure which has the lowest breakdown voltage for a given technology is incorporated into the SCR enabling a SCR trigger voltage determined by the lowest breakdown-structure.

Low voltage triggering semiconductor controlled rectifiers

Two techniques are presented for optimizing the parametric yield of digital MOS circuit blocks for VLSI designs. The first is based on quasi-Newton methods and utilizes the gradient of the yield. A novel technique for computing this yield gradient is derived and algorithms for its implementation are discussed. Geometrical considerations motivate the second method which formulates the problem in terms of a minimax problem. Both yield optimization techniques utilize transient sensitivity information from circuit simulations. Encouraging results have been obtained thus far; several circuit examples are included to demonstrate these techniques. >

P. Yang

Papers

A Monte Carlo approach for power estimation

Multilevel metal capacitance models for CAD design synthesis systems

Probabilistic simulation for reliability analysis of CMOS VLSI circuits

Low voltage triggering semiconductor controlled rectifiers

Parametric yield optimization for MOS circuit blocks