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http://user.it.uu.se/~jarst116/slides/week4.pdf

Graph-Based Algorithms for Boolean Function Manipulation

Design and Analysis ofFault-Tolerant Digital Systems: B. W. JOHNSON (Addison Wesley, 1989,577 pp., £41.35) The book provides an introduction to the important aspects of designing fault-tolerant systems, and an evaluation of how well the reliability goals have been achieved. The book is mainly oriented towards a final year undergraduate course on fault-tolerant computing, primarily with an implementation bias. In chapters 1 and 2, definitions and basic terminology are covered, which sets the stage for the remaining chapters, and provides the background and motivation for the remainder of the book. Chapter 3 provides a thorough analysis of fault-tolerance techniques and concepts. This chapter in particular is remarkably well written, covering the issues of hardware and information redundancy, which form the mainstay offault-tolerant computing. Subsequent chapters on the use and evaluation of the various approaches illustrate the principles as they have been put into practice. At the end of chapter 5, small projects that allow the reader to apply the material presented in the preceding chapters are included. The resurgence of interest in fault-tolerance with the emergence of VLSI is the theme of chapter 6, focussing on designing fault-tolerant systems in a VLSI environment. The problems and opportunities presented by VLSI are discussed and the use of redundancy techniques in order to enhance manufacturing yield and to provide in-service reliability are reviewed. The final chapter covers testing, design for testability and testability analysis, which must be considered during each phase of the design process to guarantee that resulting designs can be thoroughly tested. Each chapter is followed by a summary of the key issues and concepts presented therein, and a separate list of references, which makes it easily readable. In addition, there is a reading list with more comprehensive and specialised references devoted to each chapter. Overall, the book is well written, and contains a great deal of information in 577 pages. The book has a definite implementation bias, and draws considerably on the author's experience in industry, particularly reflected in the projects accompanying chapter 5. The book should be a useful addition to a library, and a suitable text to accompany a lecture course on fault-tolerant computing. R. RAMASWAMI, Department ofComputation, UMIST

Book Review: Design and Analysis of Fault-Tolerant Digital SystemsDesign and Analysis of Fault-Tolerant Digital Systems: JohnsonB. W. (Addison Wesley, 1989, 577 pp., £41.35)

Asynchronous Circuit Design

: A given switching function of n variables can frequently be decomposed into a composite function of several essentially simpler switching functions. Such decompositions lead to designs of more economical switching circuits to realize the given switching function. Ashenhurst's chart method is generalized to nondisjunctive decompositions by means of the don't care conditions. This extension provides an effective method of constructing all decompositions of switching functions. (Author)

On the decomposition of switching functions

A robust asynchronous full adder design corresponding to early output logic, synthesized using the elements of a standard cell library is presented in this paper. As the name suggests, the adder ensures gate orphan freedom and neatly fits into the self-timed system architecture. In comparison with many of the indicating full adder designs, which can be embedded in the self-timed system, it is found that the proposed full adder enables reduction in latency by 20.7%, occupies lesser area by 15.4% and features minimized average power dissipation by 8.6% against the best design metrics of its counterparts. These design estimates correspond to simulation results of the 32-bit carry-ripple adder circuit; derived by targeting a high-speed 130nm bulk CMOS process technology. Also, the proposed full adder facilitates a faster reset and the return-to-zero for the fundamental carry-propagate topology is achieved with only two full adder delays.

/pdf/a-robust-asynchronous-early-output-full-adder-3yghecugz9.pdf

A robust asynchronous early output full adder

For digital system designs, triple modular redundancy (TMR), which is a 3-tuple version of N-modular redundancy is widely preferred for many mission-control and safety-critical applications. The TMR scheme involves two-times duplication of the simplex system hardware, with a majority voter ensuring correctness provided at least two out of three copies of the system remain operational. Thus the majority voter plays a pivotal role in ensuring the correct operation of the system. The fundamental assumption implicit in the TMR scheme is that the majority voter does not become faulty, which may not hold well for implementations based on latest technology nodes with dimensions of the order of just tens of nanometers. To overcome the drawbacks of the classical majority voter some new voter designs were put forward in the literature with the aim of enhancing the fault tolerance. However, these voter designs generally ensure the correct system operation in the presence of either a faulty function module or the faulty voter, considered only in isolation. Since multiple faults may no longer be excluded in the nanoelectronics regime, simultaneous fault occurrences on both the function module and the voter should be considered, and the fault tolerance of the voters have to be analyzed under such a scenario. In this context, this article proposes a new fault-tolerant majority voter which is found to be more robust to faults than the existing voters in the presence of faults occurring internally and/or externally to the voter. Moreover, the proposed voter features less power dissipation, delay, and area metrics based on the simulation results obtained by using a 32/28nm CMOS process.

A Fault Tolerance Improved Majority Voter for TMR System Architectures.

This article presents a biased implementation style weak-indication self-timed full adder design that is latency optimized. The proposed full adder is constructed using the delay-insensitive dual-rail code and adheres to 4-phase handshaking. Performance comparisons of the proposed full adder vis-a-vis other strong and weak-indication full adders are done on the basis of a 32-bit self-timed carry-ripple adder architecture, with the full adders and ripple carry adders realized using a 32/28nm CMOS process. The results show that the proposed full adder leads to reduction in latency by 63.3% against the best of the strong-indication full adders whilst reporting decrease in area by 10.6% and featuring comparable power dissipation. On the other hand, when compared with the existing optimized weak-indication full adder, the proposed full adder is found to minimize the latency by 25.1% whilst causing an increase in area by just 1.6%, however, with no associated power penalty.

/pdf/a-latency-optimized-biased-implementation-style-weak-4lqrell8wa.pdf

A latency optimized biased implementation style weak-indication self-timed full adder

Addition forms the basis of digital computer systems. Three novel gate level full adder designs, based on the elements of a standard cell library are presented in this work: one design involving XNOR and multiplexer gates (XNM), another design utilizing XNOR, AND, Inverter, multiplexer and complex gates (XNAIMC) and the third design incorporating XOR, AND and complex gates (XAC). Comparisons have been performed with many other existing gate level full adder realizations. Based on extensive simulations with a 32-bit carry-ripple adder implementation; targeting three process, voltage and temperature (PVT) corners of the high speed (low Vt) 65nm STMicroelectronics CMOS process, it was found that the XAC based full adder is found to be delay efficient compared to all its gate level counterparts, even in comparison with the full adder cell available in the library. The XNM based full adder is found to be area efficient, while the XNAIMC based full adder offers a slight compromise with respect to speed and area over the other two proposed adders.

/pdf/high-speed-gate-level-synchronous-full-adder-designs-1wihlejg2b.pdf

High speed gate level synchronous full adder designs

Addition forms the basis of digital computer systems A gate level self-timed full adder design, utilizing a pre-defined set of gates, available in a commercial synchronous standard cell library is discussed in this paper The proposed adder satisfies Seitz's weak-indication specifications and exhibits reduced data path delay in comparison with other existing adders, which satisfy the property of indication In terms of power and area, it is competitive to the best of other self-timed adders

/pdf/a-delay-efficient-robust-self-timed-full-adder-1dyvgplubk.pdf

Padmanabhan Balasubramanian

Papers

A robust asynchronous early output full adder

A Fault Tolerance Improved Majority Voter for TMR System Architectures.

A latency optimized biased implementation style weak-indication self-timed full adder

High speed gate level synchronous full adder designs

A delay efficient robust self-timed full adder