Showing papers by "Paul Jespers published in 1990"
Proceedings Article•
01 Sep 1990TL;DR: An untrimmed pipelined 8-bits A/D converter with both integral and differential nonlinearity error less than 1Lsb is presented.
Abstract: An untrimmed pipelined 8-bits A/D converter with both integral and differential nonlinearity error less than 1Lsb is presented. At clock frequency of 3Mhz, the circuit achieves a 1.5Msample/s data rate. Power consumption is 20mW and chip area is 2 mm2 in a 3??m CMOS technology.
26 citations
TL;DR: In this paper, the intrinsic gate-to-source capacitances of SOI n-MOSFETs at low drain-tosource voltage drop are discussed, and the results clearly show that the source and drain junction capacitance should be incorporated in small and large-signal models of small-and large-scale SOI MOSFets.
Abstract: The measurement of intrinsic gate-to-source capacitances of SOI n-MOSFETs at low drain-to-source voltage drop is discussed. Differences with classical bulk characteristics are explained in strong inversion as well as in subthreshold operation. The capacitance technique seems to offer a valuable tool for the characterization of SOI MOSFETs, supplementing static I-V measurements, since it allows the extraction, on the same device, of the front flatband voltage and of the front threshold voltage for inverted back interface. The results clearly show that the source and drain junction capacitances should be incorporated in small- and large-signal models of SOI MOSFETs. >
14 citations
01 Nov 1990
TL;DR: A new carry-free division algorithm will be described; it is based on the properties of RSD arithmetic to avoid carry propagation and uses the minimum hardware per bit i.e. one full-adder.
Abstract: A new carry-free division algorithm will be described; it is based on the properties of RSD arithmetic to avoid carry propagation and uses the minimum hardware per bit i.e. one full-adder. Its application to a 1024 bits RSA cryptographic chip will be presented. Thanks to the features of this new algorithm, high performance (8 kbits/s for 1024 bits words) was obtained for relatively small area and power consumption (80 mm2 in a 2 μm CMOS process and 500 mW at 25 MHz).
14 citations
Proceedings Article•
01 Sep 1990TL;DR: In this article, the intrinsic gate capacitances of SOI MOSFETs were measured for characterizaton purposes as well as to cast some light on dynamic floating substrate effects.
Abstract: Measurements of intrinsic gate capacitances of SOI MOSFETs are described and are shown to provide valuable information for characterizaton purposes as well as to cast some light on dynamic floating substrate effects. An accurate charge-based analytical model valid in linear operation is also presented.
1 citations
27 Nov 1990
TL;DR: The authors present the BRISC (biprocessor reduced-instruction-set computer), an integrated digital processor designed for the control of two- or three-phase power systems through vector control, e.g. to implement field-oriented or predictive control for brushless or conductive motors.
Abstract: The authors present the BRISC (biprocessor reduced-instruction-set computer), an integrated digital processor designed for the control of two- or three-phase power systems through vector control, e.g. to implement field-oriented or predictive control for brushless or conductive motors. It is also able to perform pulsewidth modulation (PWM) on its own for inverter command. The BRISC executes a user-written program, and can be used in a large range of applications, whenever the control process is expressed in terms of plane vectors and/or when PWM is required. The BRISC integrates a high functionality and is fast enough to meet the requirements of the most demanding control schemes. >