The ever-increasing demand for security in portable energy-constrained environments that lack a coherent security architecture has resulted in the need to provide energy-efficient algorithm-agile cryptographic hardware. Domain-specific reconfigurability is utilized to provide the required flexibility, without incurring the high overhead costs associated with generic reprogrammable logic. The resulting implementation is capable of performing an entire suite of cryptographic primitives over the integers modulo N, binary Galois fields and nonsupersingular elliptic curves over GF(2/sup n/), with fully programmable moduli, field polynomials and curve parameters ranging in size from 8 to 1024 bits. The resulting processor consumes a maximum of 75 mW when operating at a clock rate of 50 MHz and a 2-V supply voltage. In ultralow-power mode (3 MHz at 0.7 V) the processor consumes at most 525 /spl mu/W. Measured performance and energy efficiency indicate a comparable level of performance to previously reported dedicated hardware implementations, while providing all of the flexibility of a software-based implementation. In addition, the processor is two to three orders of magnitude more energy efficient than optimized software and reprogrammable logic-based implementations.

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An energy-efficient reconfigurable public-key cryptography processor

It is widely recognized that security issues will play a crucial role in the majority of future computer and communication systems. Central tools for achieving system security are cryptographic algorithms. For performance as well as for physical security reasons, it is often advantageous to realize cryptographic algorithms in hardware. In order to overcome the well-known drawback of reduced flexibility that is associated with traditional ASIC solutions, this contribution proposes arithmetic architectures which are optimized for modern field programmable gate arrays (FPGAs). The proposed architectures perform modular exponentiation with very long integers. This operation is at the heart of many practical public-key algorithms such as RSA and discrete logarithm schemes. We combine the Montgomery modular multiplication algorithm with a new systolic array design, which is capable of processing a variable number of bits per array cell. The designs are flexible, allowing any choice of operand and modulus. Unlike previous approaches, we systematically implement and compare several variants of our new architecture for different bit lengths. We provide absolute area and timing measures for each architecture. The results allow conclusions about the feasibility and time-space trade-offs of our architecture for implementation on Xilinx XC4000 series FPGAs. As a major practical result we show that it is possible to implement modular exponentiation at secure bit lengths on a single commercially available FPGA.

Montgomery modular exponentiation on reconfigurable hardware

This paper describes new methods for producing optimal binary signed-digit representations. This can be useful in the fast computation of exponentiations. Contrary to existing algorithms, the digits are scanned from left to right (i.e., from the most significant position to the least significant position). This may lead to better performances in both hardware and software.

Optimal left-to-right binary signed-digit recoding

Hardware architectures for public key cryptography

Today, a dozen years after the discovery of the RSA encryption algorithm [12], there are many chips available for performing RSA encryption [1] [3] [4] [5] [8] [9] [13] [15]. The purpose of this paper is to briefly describe some of the different compu- tational algorithms that have been used in the chip designs and to provide a list of all of the currently available chips. In this abstract, we will simply mention some of these computational algorithms and give references. The full paper will contain more details of these algorithms and will appear in a book on survey articles in Cryptology which is being edited by Gus Simmons and will be published by IEEE in 1990.

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A Survey of Hardware Implementations of RSA

A carry-free division algorithm is described. It is based on the properties of redundant signed digit (RSD) arithmetic to avoid carry propagation and uses the minimum hardware per bit, i.e. one full adder. Its application to a 1024-b RSA (Rivest, Shamir, and Adelman) cryptographic chip is presented. The features of this new algorithm allowed high performance (8 kb/s for 1024-b words) to be obtained for relatively small area and power consumption (80 mm/sup 2/ in a 2- mu m CMOS process and 500 mW at 25 MHz). >

A new carry-free division algorithm and its application to a single-chip 1024-b RSA processor

A new carry-free division algorithm will be described; it is based on the properties of RSD arithmetic to avoid carry propagation and uses the minimum hardware per bit i.e. one full-adder. Its application to a 1024 bits RSA cryptographic chip will be presented. Thanks to the features of this new algorithm, high performance (8 kbits/s for 1024 bits words) was obtained for relatively small area and power consumption (80 mm2 in a 2 μm CMOS process and 500 mW at 25 MHz).

/pdf/a-single-chip-1024-bits-rsa-processor-2qi66bk1yd.pdf

A single chip 1024 bits RSA processor

A 90000-transistor, 50-MIPS (million-instruction-per-second) multiprocessor chip designed for image orthogonal transform is discussed. The architectural principle, derived from a tensorial formalism, is usable for the other linear processings of multidimensional signals (e.g. n-dimensional convolution). A regularity factor of more than 99% was obtained by taking advantage of systolic principles at both chip and bit levels. >

A class of multiprocessors for real-time image and multidimensional signal processing

A systolic-like circuit, part of a real-time image multiprocessor will be presented. The chip which is used in 2_D orthogonal transform applications has been designed as a general purpose matrix product processor. A prototype was processed in a 3 ?m CMOS single metal technology. The transistor density is approximatively 875/mm2.

http://ieeexplore.ieee.org/iel5/5434908/5434909/05434924.pdf

A Systolic-Like Multiprocessor for Real-Time Orthogonal Transform on TV Images

A 50-MIPS (million-instruction-per-second) 90000-transistor CMOS multiprocessor chip is described. It has been designed as a building block for orthogonal transforms of TV images in a bandwidth-reduction system. 64 processing elements (serial parallel multipliers) are assembled in a systolic-like architecture. Because of its modularity, the chip can be used for matrix products of arbitrary size. >

http://ieeexplore.ieee.org/iel2/737/826/00020823.pdf

Etienne Vanzieleghem

Papers

A new carry-free division algorithm and its application to a single-chip 1024-b RSA processor

A single chip 1024 bits RSA processor

A class of multiprocessors for real-time image and multidimensional signal processing

A Systolic-Like Multiprocessor for Real-Time Orthogonal Transform on TV Images

A 50 MIPS multiprocessor chip for image processing