Showing papers by "Paul Jespers published in 2008"
TL;DR: Redundancy in the output code as an instrument to reduce the impact of nonidealities in different architectures of two-step analog to digital converters (ADC) is investigated and two distinct models are proposed: the behavioral model and the circuit model.
Abstract: Redundancy in the output code as an instrument to reduce the impact of nonidealities in different architectures of two-step analog to digital converters (ADC) is investigated. The CRZ converters, which are the converters obtained from the conventional CR architecture with addition of Z extra decision levels, are formalized and compared with the RSD converter. Two distinct models are proposed to investigate separately, by means of system level simulations, the impact of each source of error: the behavioral model and the circuit model. The first one is intended to give an intuitive understanding of how redundancy improves the output response of this class of converters, while the latter is introduced to find, at an early design stage, the optimum sizing of passive components meeting a given resolution. Simulation results from both models are discussed and the different performances of the various converters are evaluated with respect to power, area, and effective resolution.
11 citations
04 May 2008
TL;DR: A circuit model capable of providing an estimate of the required sizes for passive components for a given accuracy was developed, and represents an useful design tool, providing a way to calculate important figures of merit of the different ADCs.
Abstract: Redundancy in the output code, as instrument to reduce the impact of non-idealities in different architectures of two-step A to D converters, is investigated. A circuit model capable of providing an estimate of the required sizes for passive components for a given accuracy was developed. Such model represents an useful design tool, providing a way to calculate important figures of merit (area, power, ENOB, SNR, large-signal behavior) of the different ADCs. System-level simulation results are provided and discussed.
01 Sep 2008
TL;DR: The gm/ID sizing methodology is applied to the sizing of low-power low-voltage CMOS circuits like the Miller Op.
Abstract: The gm/ID sizing methodology. Sizing the Intrinsic Gain Stage by means of experimental data or a model like the E.K.V./A.C.M. model. Sizing short channel devices with parameters that are functions of bias conditions. Parameter acquisition, accuracy, examples. Application to the sizing of low-power low-voltage CMOS circuits like the Miller Op. Amp, Barranco's current sources, etc.