Showing papers by "Paul S. Ho published in 2015"

Through-silicon via stress characteristics and reliability impact on 3D integrated circuits

Abstract: Three-dimensional (3D) integration has emerged as a potential solution to the wiring limits imposed on chip performance, power dissipation, and packaging form factor beyond the 14 nm technology node. In 3D integrated circuits (ICs), the through-silicon via (TSV) is a critical element connecting die-to-die in the integrated stack structure. The thermal expansion mismatch between copper (Cu) vias and silicon (Si) can induce complex stresses in TSV structures to drive interfacial failure and Cu extrusion, degrading the performance and reliability of 3D interconnects. This article reviews current studies on thermal stresses and their effects on reliability of TSV structures. Recent results from measurements of stress and plasticity characteristics of Cu TSV structures are reviewed, including wafer curvature, micro-Raman spectroscopy, and synchrotron x-ray microdiffraction techniques. The effects of the Cu microstructure on stress and reliability, particularly on via extrusion and the device keep-out zone in TSV structures, are discussed. Based on the analysis of the reliability impact, we explore the potential of material and processing optimization to build reliable TSV structures for 3D ICs.

Co Liner Impact on Microstructure of Cu Interconnects

Abstract: The microstructure of Cu interconnects fabricated with Ta and Co liner materials had been examined by transmission electron microscopy and correlated to the electrical characteristics. Cu lines of 40 nm width were fabricated on 300 mm Si wafers by conventional CMOS backend processing. Electrical measurements performed immediately after fabrication of these Cu lines showed similar electrical resistance for Co and Ta liners. However, a 2.5-hour anneal at 375 ◦ C led to 5% more resistance reduction for Cu lines with the Ta liner than with the Co liner. Microstructure analyses showed that Cu lines with the Ta liner had 24% coherent 3 grain boundaries while lines with the Co liner yielded only 6% of coherent grain boundaries. In addition, Cu with Ta liner had a stronger � 111� texture along the line width direction. However, the overall grain size distribution was similar between Ta and Co liners. These results suggest Co liner has some impact on Cu microstructures, which may be a root cause for the relatively higher line resistance.

JSS FOCUS ISSUE ON ADVANCED INTERCONNECTS :M ATERIALS ,P ROCESSING, AND RELIABILITY Co Liner Impact on Microstructure of Cu Interconnects

Abstract: The microstructure of Cu interconnects fabricated with Ta and Co liner materials had been examined by transmission electron microscopy and correlated to the electrical characteristics. Cu lines of 40 nm width were fabricated on 300 mm Si wafers by conventional CMOS backend processing. Electrical measurements performed immediately after fabrication of these Cu lines showed similar electrical resistance for Co and Ta liners. However, a 2.5-hour anneal at 375 ◦ C led to 5% more resistance reduction for Cu lines with the Ta liner than with the Co liner. Microstructure analyses showed that Cu lines with the Ta liner had 24% coherent 3 grain boundaries while lines with the Co liner yielded only 6% of coherent grain boundaries. In addition, Cu with Ta liner had a stronger � 111� texture along the line width direction. However, the overall grain size distribution was similar between Ta and Co liners. These results suggest Co liner has some impact on Cu microstructures, which may be a root cause for the relatively higher line resistance.

Effect of Cu grain boundary sliding on TSV extrusion

Abstract: This study investigates the effect of grain boundary sliding (GBS) and material properties on the extrusion of through-silicon via. A finite element model is set up to evaluate via extrusion during thermal cycling taking into account the actual grain structures near the via top. The elastic anisotropy and plasticity are considered for each Cu grain, and the grain orientation obtained from experimental measurements is directly mapped into the FEA model. GBS is described by a cohesive zone model based on a frictional traction separation relationship. Based on GBS, the via extrusion behavior is deduced for two different Cu/Si interfacial conditions: fully bonded and free sliding, corresponding to the upper and lower bounds of the extrusion. In each case, the effect of GBS is evaluated by analyzing the plasticity and extrusion profiles. The results indicate that GBS plays a dominant role in determining the magnitude and profile of via extrusion.

Mechanistic Study of Plasma Damage of Low k

Abstract: Plasma damage to low k dielectric materials was investigated from a mechanistic point of view. Low k dielectric films were treated by plasma Ar, O2, N2/H2, N2 and H2 in a standard RIE chamber and the damage was characterized by Angle Resolved X-ray Photoelectron Spectroscopy (ARXPS), X-Ray Reflectivity (XRR), Fourier Transform Infrared Spectroscopy (FTIR) and Contact Angle measurements. Both carbon depletion and surface densification were observed on the top surface of damaged low k materials while the bulk remained largely unaffected. Plasma damage was found to be a complicated phenomenon involving both chemical and physical effects, depending on chemical reactivity and the energy and mass of the plasma species. A downstream hybrid plasma source with separate ions and atomic radicals was employed to study their respective roles in the plasma damage process. Ions were found to play a more important role in the plasma damage process. The dielectric constant of low k materials can increase up to 20% due to plasma damage and we attributed this to the removal of the methyl group making the low k surface hydrophilic. Annealing was generally effective in mitigating moisture uptake to restore the k value but the recovery was less complete for higher energy plasmas. Quantum chemistry calculation confirmed that physisorbed water in low k materials induces the largest increase of dipole moments in comparison with changes of surface bonding configurations, and is primarily responsible for the dielectric constant increase.

Investigation of thermo-mechanical stresses and reliability of 3D die-stack structures by synchrotron x-ray micro-diffraction

Abstract: In this work, thermo-mechanical stresses and reliability of 3D die-stack structures developed for the Hybrid Memory Cube (HMC) technology are investigated using experiments and modeling analysis. Synchrotron x-ray micro-diffraction measurements are used to directly measure the stress distribution around Cu vias in different die levels. High resolution stress mappings are obtained and verified by finite element analysis (FEA). The FEA is applied to estimate the stress effect on device mobility changes and the warpage of the integrated structure.