개인정보 보호법 : private information

Using FinFET for designing of SRAM cells has shown a great deal of advantages over planar bulk devices due to the additional control on the gates and due to fully depleted behavior. The improvements have been noted in sub-threshold slope, drive currents, short-channel effects and mismatches. As the memories become denser, the stability of the SRAM cells becomes a point of great concern. This calls for the need of assist circuitry for improving the reliability and stability of the cells. In this work, a write assist technique is discussed to improve the stability of the device. This design decreases the WL CRIT drastically and reduces the write delay of the cell. The simulations have been carried out on HSPICE with 32 nm PTM libraries for FinFET.

Design and analysis of 6T SRAM cell with NBL write assist technique using FinFET

FinFET devices are extensively investigated due to the prospects for application in the sub-100nm CMOS integrated circuits fabrication. Small size of the FinFETs and the properties of technological processes strongly influence their electrical characteristics. The random variations of the characteristics lead to a mismatch effect critical from the viewpoint of design and fabrication. In the paper different types of the variations of FinFET characteristics are discussed. The considerations are illustrated with measurement data of a series of devices and with distributions of the parameters extracted from these data. Possible effect of the parameter variability on digital cell parameters is analyzed.

Fluctuations of electrical characteristics of FinFET devices

A methodology of FinFETs characterization based on electrical characteristics of FinFET devices have has been proposed. The measured channel and gate current vs voltage characteristics of sets of devices with different fin width have been used for evaluation of the FinFETs parameters. Namely, a channel current data have been used for estimation of threshold voltage, transconductance coefficient, effective fin width, subthreshold slope and degradation of effective mobility. Top and side components of gate current have been extracted. The results have been illustrated by numerical simulations. Finally, future works on FinFETs characterization have been proposed.

Electrical characterization of FinFETS

New threshold voltage definition for undoped symmetrical DG MOSFET

A new analytical drain current model is proposed for symmetrical undoped double gate MOS transistors. It contains no fitting parameters and is physically-based.

https://ieeexplore.ieee.org/iel5/6218252/6225738/06226274.pdf

Pawel Salek

Papers

Fluctuations of electrical characteristics of FinFET devices

Electrical characterization of FinFETS

New threshold voltage definition for undoped symmetrical DG MOSFET

Analytical drain current core model for undoped double gate MOS transistor