Showing papers by "Payam Heydari published in 2021"

An mm-Wave Scalable PLL-Coupled Array for Phased-Array Applications in 65-nm CMOS

Abstract: A new two-element phase-locked loop (PLL)-coupled array for the implementation of millimeter-wave (mm-wave) and subterahertz (sub-THz) phased arrays is presented. This architecture avoids using lossy phase shifter to create the required phase shift between the adjacent elements in a phased-array system. The required phase shift is generated by utilizing a dual nested loop PLL. The two PLL loops work together to stabilize the frequency and create the required phase shift. Moreover, it can be scaled simply by adding more unit cells to the architecture. A 112–121-GHz two-element phased array is designed and fabricated in a standard 65-nm CMOS process. It consumes 147-mW power and provides a phase shift of 46.7° ranging from 58.53° to 105.2° at 117 GHz.

Terahertz Integrated Circuits and Systems for High-Speed Wireless Communications: Challenges and Design Perspectives

Abstract: This paper presents challenges and design perspectives for terahertz (THz) integrated circuits and systems. THz means different things to different people. From International Telecommunication Union (ITU) perspective, THz radiation primarily means frequency range from 300 – 3000 GHz. However, recently, a more expansive definition of THz has emerged that covers frequencies from 100 GHz to 10 THz, which includes sub-THz (100 – 300 GHz), ITU-defined THz frequencies. This definition is now commonly used by communication theorists, and since this paper is intended for people with a wide variety of expertise in system and circuit design, we have adopted the latter definition. The paper brings to the open unmitigated shortcomings of conventional transceiver architectures for multi gigabit-per-second wireless applications, unfolds challenges in designing THz transceivers, and provides pathways to address these impediments. Furthermore, it goes through design challenges and candidate solutions for key circuit blocks of a transceiver including front-end amplifiers, local oscillator (LO) circuit and LO distribution network, and antennas intended for frequencies above 100 GHz.

Transceivers for 6G Wireless Communications: Challenges and Design Solutions

Abstract: Sixth-generation (6G) wireless communication has begun to emerge to push the speed and data rate achieved in 5G by, at least, an order of magnitude, fulfilling the goal of fully scalable and adaptive wireless infrastructures with small cells interconnected through distributed base-stations and relay networks. Wireless transceivers, as the core enabling ingredient of 6G, should be able to handle tens of gigabit-per-second data rate in ways that are both power and spectrally efficient. The paper brings to the open the unmitigated shortcomings of conventional transceiver architectures for above 50 gigabit-per-second wireless applications, unfolds challenges in designing transceivers for 6G (and beyond) and provides pathways to address these impediments. Furthermore, it goes through design challenges and candidate solutions for key circuit blocks of a transceiver including front-end amplifiers, local oscillator (LO) circuit and LO distribution network, and antennas intended for frequencies above 100 GHz.

CMOS Power-Amplifier Design Perspectives for 6G Wireless Communications

Abstract: The power amplifier (PA) for future 6G sub-THz wireless transmitters needs to offer wide bandwidth, high output power and reliable stability. This article, for the first time, studies the notion of wideband operation in sub-THz PAs incorporating neutralization techniques. Quantitative analyses are conducted to better understand the trade-offs among G max , stability K f , and the bandwidth for a widely adopted differential pair under (over) neutralization. Next, a comparative study for transmission-line (T-line)-based and transformer-based matching networks is undertaken to give insights to the design of inter-stage matching networks. It is shown that transformer-based matching networks essentially introduce multi-stagger tuning, thereby leading to higher operation bandwidth suitable for 6G applications.

An LO Leakage Suppression Technique for Blocker-Tolerant Wideband Receivers With High- Q Selectivity at RF Input

Abstract: A wideband blocker-tolerant receiver (RX) employing a novel local oscillator (LO) leakage suppression technique is presented. At the core of this RX, lies a bandpass common-gate structure that realizes high- $Q$ selectivity directly at RF input while greatly suppressing LO leakage coupled to the RX input. The RX prototype, manufactured in a 45-nm CMOS SOI process, achieves wideband tunable high- $Q$ selectivity from 0.2 to 2 GHz, while the LO leakage stays well below −80 dBm. The noise figure is better than 2.5 dB and degrades to 6.7 dB with a 0-dBm blocker at 80-MHz offset frequency. The measured out-of-band IIP2 and IIP3 at 100-MHz offset frequency are +60 and +14 dBm, respectively. The RX consumes up to 95 mW of total power at 2 GHz and occupies 1.05 mm 2 of active area.

Energy Efficient 100+ GHz Transceivers Enabling Beyond-5G Wireless Communications

Abstract: Portable computing devices handling multi gigabit-per-second (Gb/s) data rates are anticipated to enter the wireless market with the rise of the 5G protocol in the future. The recent allocation of the above-100-GHz band by the Federal Communications Commission creates a great opportunity for developing wireless networks with distributed base station nodes targeting high data rates. This ever-in-creasing need for higher data rates calls for novel transceiver architectures that address fundamental shortcomings of the conventional designs and can achieve tens of Gb/s speed with high spectral efficiency. This article presents an overview of design challenges and opportunities in regard to implementation of energy efficient 100+ GHz wireless transceivers and opportunities for research and development in this emerging area.

An Analysis of CMRR Degradation in Multi-Channel Biosignal Recording Systems

Abstract: Multi-channel biosignal recording systems that employ a shared-reference scheme and achieve high common-mode rejection ratio (i.e., CMRR > 80dB) have been reported in recent works. While it is well-understood that a shared-reference scheme causes impedance mismatch at the input terminals of bioamplifier, and thus limits the maximum achievable CMRR, a theoretical study that can provide quantitative assessment of this source of degradation is still lacking. This brief provides an equivalent electrical circuit model of the input interface consisting of an electrode array and bioamplifiers, followed by a complete analysis to formulate the CMRR degradation. Simulation results based on a previously designed and fabricated 32-channel neural recording front-end in a 180nm CMOS process are presented, exhibiting close agreement with the theory.

A Comprehensive Analysis of Charge-Pump-Based Multi-Stage Multi-Output DC-DC Converters

Abstract: This paper presents an analytical model for calculating the output voltage and the power efficiency of multi-stage multi-output (MSMO) DC-DC converters (DDC) that use charge pump cells for boosting the voltage. Various cases such as multi-output current consumption and its effects on the output voltage and the power efficiency are studied. Based on the model, a tapered design approach is proposed that can bolster the power efficiency and lower the output voltage drop of MSMO DDCs. Moreover, a charge-pump-based DDC is introduced and designed to verify the proposed model. Simulation results using a standard high-voltage 180-nm CMOS technology affirms the accuracy of the presented model.

A 40V Voltage-Compliance 12.75mA Maximum-Current Multipolar Neural Stimulator Using Time-Based Charge Balancing Technique Achieving 2mV Precision

Abstract: Electrical brain stimulation (EBS) is a technique to stimulate neurons by current pulses. Charge accumulation due to these pulses leads to voltage build up, causing electrode corrosion and tissue damage. To ensure the safety and longevity of EBS operation, various charge balancing (CB) methods have been introduced.

Noise Analysis of Passive Sampling Mixers Using Auto- and Cross-Correlation Functions

Abstract: An analysis of noise in passive sampling mixers is presented, which is based on derivations of auto- and cross- correlation functions that capture statistical co-dependence of noise components during the tracking and hold phases of sampling mixer operation. This study accurately predicts the noise-folding due to cyclostationarity of the sampling noise of the mixer. As will be discussed, notwithstanding its simple form, the proposed approach yields an accurate noise model, which will simplify to existing noise models presented by prior work under their adopted assumptions.

Microfluidic Rapid Prototype Enzymatic Biofuel Cell Based on a Nanocomposite

Abstract: Here, a low-cost glucose/O2 Y-shaped microfluidic biofuel cell was developed using a printed circuit board (PCB) for microelectrode construction. A double-side tape based on the pressure-sensitive adhesive (PSA) was used for microchannel fabrication. A nanocomposite consists of reduced graphene oxide (RGO), gold nanoparticles (AuNPs), and poly neutral red (PNR) connect to enzymes was applied on the copper electrode surface. The Aspergillus niger glucose oxidase enzyme and Mytheliophthora thermophile laccase were used to prepare the modified anodic and cathodic electrodes. Different procedures such as cyclic voltammetry (CV), scanning electron microscope (SEM) coupled with energy-dispersive x-ray spectroscopy (EDX), and atomic force microscopy (AFM) were scanned the modified electrodes. SEM/EDX microanalysis was showed the structural and morphological properties of the proposed nanocomposite. The biofuel cell performance was demonstrated the maximum power density of 36 μW cm−2, an open-circuit voltage (OCV) of 0.5 V with a flow rate of 50 L min-1. The proposed rapid technique with RGO/AuNPs/PNR bioelectrodes is a good approach for finding low-cost microfluidic biofuel cell.

Decoding of the Walking States and Step Rates from Cortical Electrocorticogram Signals

Abstract: Brain-computer interfaces (BCIs) have shown promising results in restoring motor function to individuals with spinal cord injury. These systems have traditionally focused on the restoration of upper extremity function; however, the lower extremities have received relatively little attention. Early feasibility studies used noninvasive electroencephalogram (EEG)-based BCIs to restore walking function to people with paraplegia. However, the limited spatiotemporal resolution of EEG signals restricted the application of these BCIs to elementary gait tasks, such as the initiation and termination of walking. To restore more complex gait functions, BCIs must accurately decode additional degrees of freedom from brain signals. In this study, we used subdurally recorded electrocorticogram (ECoG) signals from able-bodied subjects to design a decoder capable of predicting the walking state and step rate information. We recorded ECoG signals from the motor cortices of two individuals as they walked on a treadmill at different speeds. Our offline analysis demonstrated that the state information could be decoded from >16 minutes of ECoG data with an unprecedented accuracy of 99.8%. Additionally, using a Bayesian filter approach, we achieved an average correlation coefficient between the decoded and true step rates of 0.934. When combined, these decoders may yield decoding accuracies sufficient to safely operate present-day walking prostheses.