The SPLASH-2 suite of parallel applications has recently been released to facilitate the study of centralized and distributed shared-address-space multiprocessors. In this context, this paper has two goals. One is to quantitatively characterize the SPLASH-2 programs in terms of fundamental properties and architectural interactions that are important to understand them well. The properties we study include the computational load balance, communication to computation ratio and traffic needs, important working set sizes, and issues related to spatial locality, as well as how these properties scale with problem size and the number of processors. The other, related goal is methodological: to assist people who will use the programs in architectural evaluations to prune the space of application and machine parameters in an informed and meaningful way. For example, by characterizing the working sets of the applications, we describe which operating points in terms of cache size and problem size are representative of realistic situations, which are not, and which re redundant. Using SPLASH-2 as an example, we hope to convey the importance of understanding the interplay of problem size, number of processors, and working sets in designing experiments and interpreting their results.

/pdf/the-splash-2-programs-characterization-and-methodological-14b6i8va45.pdf

The SPLASH-2 programs: characterization and methodological considerations

We present the internals of QEMU, a fast machine emulator using an original portable dynamic translator. It emulates several CPUs (x86, PowerPC, ARM and Sparc) on several hosts (x86, PowerPC, ARM, Sparc, Alpha and MIPS). QEMU supports full system emulation in which a complete and unmodified operating system is run in a virtual machine and Linux user mode emulation where a Linux process compiled for one target CPU can be run on another CPU.

/pdf/qemu-a-fast-and-portable-dynamic-translator-xpb07ophlg.pdf

QEMU, a fast and portable dynamic translator

The determination of upper bounds on execution times, commonly called worst-case execution times (WCETs), is a necessary step in the development and validation process for hard real-time systems. This problem is hard if the underlying processor architecture has components, such as caches, pipelines, branch prediction, and other speculative components. This article describes different approaches to this problem and surveys several commercially available tools1 and research prototypes.

/pdf/the-worst-case-execution-time-problem-overview-of-methods-2kdq3gxkoy.pdf

The worst-case execution-time problem—overview of methods and survey of tools

http://www.inf.ufes.br/~luciac/comcie/JFNK-Knoll.pdf

Jacobian-free Newton-Krylov methods: a survey of approaches and applications

The most exciting development in parallel computer architecture is the convergence of traditionally disparate approaches on a common machine structure. This book explains the forces behind this convergence of shared-memory, message-passing, data parallel, and data-driven computing architectures. It then examines the design issues that are critical to all parallel architecture across the full range of modern design, covering data access, communication performance, coordination of cooperative work, and correct implementation of useful semantics. It not only describes the hardware and software techniques for addressing each of these issues but also explores how these techniques interact in the same system. Examining architecture from an application-driven perspective, it provides comprehensive discussions of parallel programming for high performance and of workload-driven evaluation, based on understanding hardware-software interactions.


* synthesizes a decade of research and development for practicing engineers, graduate students, and researchers in parallel computer architecture, system software, and applications development

* presents in-depth application case studies from computer graphics, computational science and engineering, and data mining to demonstrate sound quantitative evaluation of design trade-offs 

* describes the process of programming for performance, including both the architecture-independent and architecture-dependent aspects, with examples and case-studies

* illustrates bus-based and network-based parallel systems with case studies of more than a dozen important commercial designs

Table of Contents

1 Introduction 
2 Parallel Programs 
3 Programming for Performance 
4 Workload-Driven Evaluation 
5 Shared Memory Multiprocessors 
6 Snoop-based Multiprocessor Design 
7 Scalable Multiprocessors
8 Directory-based Cache Coherence
9 Hardware-Software Tradeoffs 
10 Interconnection Network Design 
11 Latency Tolerance 
12 Future Directions 
APPENDIX A Parallel Benchmark Suites

Parallel Computer Architecture: A Hardware/Software Approach

Multi-cores are here to stay, whether we like it or not. With a quadrupling of the core count every three years, chips with hundreds of processor cores are projected in the next decade. The question is, how much of their computational power can be unleashed, what it will take to unleash it, and how best can research accelerate progress? Several decades of research in multiprocessing has not really made the case. On the other hand, now that coarse-grain parallelism seems to be our only hope and the computing landscape is arguably different, opportunities may arise. The following cross-cutting issues will be debated in this panel with the hope of distilling new avenues for parallelism exploitation: Is the computing landscape (technology, applications, and market) today sufficiently different to exploit multiprocessors from what it was in the past? If yes, in what sense? If not, why? Do we need more research in multiprocessing given past work? If yes, what are the biggest challenges? If not, state the reasons. Will progress in software/architecture make it possible to make sequential languages prevail? If yes, what are the top priorities in research to make that happen? If not, what are the visions for a parallel-language paradigm shift and what are the major challenges in software/architecture research to accelerate uptake in the programming community? Would multi-disciplinary research (across the applications, algorithms, software, and architecture areas) be a good way to accelerate developments? Then, what areas should interact more closely and with what goals in mind?

IPDPS Panel: Is the Multi-Core Roadmap going to Live Up to its Promises?

Invited Program.- Supercomputing for the Future, Supercomputing from the Past (Keynote).- I Multithreaded and Multicore Processors.- MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing.- rMPI: Message Passing on Multicore Processors with On-Chip Interconnect.- Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE.- IIa Reconfigurable - ASIP.- BRAM-LUT Tradeoff on a Polymorphic DES Design.- Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array.- Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP.- IIb Compiler Optimizations.- Fast Bounds Checking Using Debug Register.- Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis.- An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems.- III Industrial Processors and Application Parallelization.- Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions.- Experiences with Parallelizing a Bio-informatics Program on the Cell BE.- Drug Design Issues on the Cell BE.- IV Power-Aware Techniques.- Coffee: COmpiler Framework for Energy-Aware Exploration.- Integrated CPU Cache Power Management in Multiple Clock Domain Processors.- Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation.- V High-Performance Processors.- The Significance of Affectors and Affectees Correlations for Branch Prediction.- Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator.- LPA: A First Approach to the Loop Processor Architecture.- VI Profiles: Collection and Analysis.- Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation Algorithm.- Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and Accuracy.- Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior.- VII Optimizing Memory Performance.- MLP-Aware Dynamic Cache Partitioning.- Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture.- Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory.- Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache.

High performance embedded architectures and compilers : Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008 : proceedings

As chip multiprocessors with simultaneous multithreaded cores are becoming commonplace, there is a need for simple approaches to exploit thread-level parallelism. In this paper, we consider thread-level speculation as a means to reap thread-level parallelism out of application binaries. We first investigate the trade-offs between scheduling speculative threads on the same core and on different cores. While threads contend for the same resources using the former approach, the latter approach is plagued by the overhead for inter-core communication. Despite the impact of resource contention, our detailed simulations show that the first approach provides the best performance due to lower inter-thread communication cost. The key contribution of the paper is the proposed design and evaluation of the dual-thread speculation system. This design point has very low complexity and reaps most of the gains of a system.

Dual-thread speculation: a simple approach to uncover thread-level parallelism on a simultaneous multithreaded processor

Comparative evaluation of latency-tolerating and -reducing techniques for hardware-only and software-only directory protocols

Transactional memory systems trade ease of programming with runtime performance losses in handling transactions. This paper focuses on starvation effects that show up in systems where unordered transactions are committed on a demand-driven basis. Such simple commit arbitration policies are prone to starvation. The design issues for commit arbitration policies are analyzed and novel policies that reduce the amount of wasted computation due to roll-back and, most importantly, that avoid starvation are proposed. We analyze in detail how to incorporate them in a TCC-like transactional memory protocol. The proposed schemes have no impact on the common-case performance and add quite modest complexity to the baseline protocol.

/pdf/starvation-free-transactional-memory-system-protocols-2szzzhu8r7.pdf

Per Stenström

Papers

IPDPS Panel: Is the Multi-Core Roadmap going to Live Up to its Promises?

High performance embedded architectures and compilers : Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008 : proceedings

Dual-thread speculation: a simple approach to uncover thread-level parallelism on a simultaneous multithreaded processor

Comparative evaluation of latency-tolerating and -reducing techniques for hardware-only and software-only directory protocols

Starvation-free transactional memory-system protocols