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Showing papers by "Peter Fischer published in 2007"


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TL;DR: The International Linear Collider (ILC) is a 200-500 GeV center-of-mass high-luminosity linear electron-positron collider, based on 1.3 GHz superconducting radio-frequency (SCRF) accelerating cavities.
Abstract: The International Linear Collider (ILC) is a 200-500 GeV center-of-mass high-luminosity linear electron-positron collider, based on 1.3 GHz superconducting radio-frequency (SCRF) accelerating cavities. The ILC has a total footprint of about 31 km and is designed for a peak luminosity of 2x10^34 cm^-2 s^-1. The complex includes a polarized electron source, an undulator-based positron source, two 6.7 km circumference damping rings, two-stage bunch compressors, two 11 km long main linacs and a 4.5 km long beam delivery system. This report is Volume III (Accelerator) of the four volume Reference Design Report, which describes the design and cost of the ILC.

55 citations



Journal ArticleDOI
TL;DR: In this article, a DEPFET-based sensor module for the International Linear Collider (ILC) vertex detector is described and the design of the latest generation of switch-chip steering chips is presented.
Abstract: Large arrays of depleted field effect transistor (DEPFET) detector elements are one possible technology for the vertex detector of the planned International Linear Collider. The main challenges are the production of large ( 10 cm 2 ) devices with an average thickness of around 100 μ m (silicon) and their fast column parallel readout. This paper describes in some detail how a DEPFET based sensor module could be built and presents the design of the latest generation of ‘Switcher’ steering chips.

33 citations


Journal ArticleDOI
TL;DR: In this article, a DEPleted Field Effect Transistor (DEPFET) sensor is integrated on a sidewards depleted p-on-n silicon detector, thereby combining the advantages of a fully depleted silicon sensor with in-pixel amplification.
Abstract: In a DEPleted Field Effect Transistor (DEPFET) sensor a MOSFET is integrated on a sidewards depleted p-on-n silicon detector, thereby combining the advantages of a fully depleted silicon sensor with in-pixel amplification. A 450 μm thick DEPFET was tested in a testbeam. The S/N was found to be larger than 110. The position resolution is better than 5 μm. At a seed cut of 7σ, the efficiency and purity are both close to 100%. In the readout chip a zero-suppression capability is implemented. The functionality was demonstrated using a radio-active source. The predicted impact parameter resolution of a 50 μm thick DEPFET vertex detector, is much better than required for the International Linear Collider (ILC).

27 citations


DOI
01 Jan 2007
TL;DR: In this article, the SWITCHER3 chip has been developed for the purpose of applying voltage steps of up to 10V to gate and clear rows, and it contains 128 channels, a flexible sequencer and relies on bump bonding.
Abstract: DEPFET Pixel sensor matrices consist of regular arrangements of DEPFETs. They are read out sequentially by enabling individual gate rows so that the currents in the drain columns reflect the pixel charge. Specialized chips are required to apply voltage steps of up to 10V to gateand clear rows. The radiation tolerant SWITCHER3 chip has been developed for that purpose. It contains 128 channels, a flexible sequencer and relies on bump bonding. The latest drain readout architecture is briefly introduced.

17 citations


Book ChapterDOI
05 Jan 2007

6 citations