As technology scales, variability in transistor performance continues to increase, making transistors less and less reliable. This creates several challenges in building reliable systems, from the unpredictability of delay to increasing leakage current. Finding solutions to these challenges require a concerted effort on the part of all the players in a system design. This article discusses these effects and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.

Designing reliable systems from unreliable components: the challenges of transistor variability and degradation

This paper presents a new multiresonant frequency-adaptive synchronization method for grid-connected power converters that allows estimating not only the positive- and negative-sequence components of the power signal at the fundamental frequency but also other sequence components at other harmonic frequencies. The proposed system is called MSOGI-FLL since it is based on both a harmonic decoupling network consisting of multiple second-order generalized integrators (MSOGIs) and a frequency-locked loop (FLL), which makes the system frequency adaptive. In this paper, the MSOGI-FLL is analyzed for single- and three-phase applications, deducing some key expressions regarding its stability and tuning. Moreover, the performance of the MSOGI-FLL is evaluated by both simulations and experiments to show its capability for detecting different harmonic components in a highly polluted grid scenario.

/pdf/multiresonant-frequency-locked-loop-for-grid-synchronization-1b1w90po2u.pdf

Multiresonant Frequency-Locked Loop for Grid Synchronization of Power Converters Under Distorted Grid Conditions

Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known technique to reduce energy in digital systems, but the effectiveness of DVFS is hampered by slow voltage transitions that occur on the order of tens of microseconds. In addition, the recent trend towards chip-multiprocessors (CMP) executing multi-threaded workloads with heterogeneous behavior motivates the need for per-core DVFS control mechanisms. Voltage regulators that are integrated onto the same chip as the microprocessor core provide the benefit of both nanosecond-scale voltage switching and per-core voltage control. We show that these characteristics provide significant energy-saving opportunities compared to traditional off-chip regulators. However, the implementation of on-chip regulators presents many challenges including regulator efficiency and output voltage transient characteristics, which are significantly impacted by the system-level application of the regulator. In this paper, we describe and model these costs, and perform a comprehensive analysis of a CMP system with on-chip integrated regulators. We conclude that on-chip regulators can significantly improve DVFS effectiveness and lead to overall system energy savings in a CMP, but architects must carefully account for overheads and costs when designing next-generation DVFS systems and algorithms.

/pdf/system-level-analysis-of-fast-per-core-dvfs-using-on-chip-3icz0auash.pdf

System level analysis of fast, per-core DVFS using on-chip switching regulators

Transient errors caused by terrestrial radiation pose a major barrier to robust system design. A system's susceptibility to such errors increases in advanced technologies, making the incorporation of effective protection mechanisms into chip designs essential. A new design paradigm reuses design-for-testability and debug resources to eliminate such errors.

https://www.eng.auburn.edu/~agrawvd/COURSE/E7770_Spr07/READ/01401773.pdf

Robust system design with built-in soft-error resilience

Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.

Characterization of soft errors caused by single event upsets in CMOS processes

A comparator to provide an output voltage indicative of comparing an input voltage with a reference voltage, where the comparator has an asymmetric frequency response. With an asymmetric frequency response, the bandwidth of the input voltage may be greater than the bandwidth of the reference voltage. A comparator includes a differential pair of transistors coupled to a current mirror and biased by a current source, where in one embodiment, a capacitor shunts the sources of the differential pair. In a second embodiment, a capacitor couples the input voltage port to the gates of the current mirror transistors. In a third embodiment, the comparator utilizes both capacitors of the first and second embodiments.

High-speed comparator with asymmetric frequency response

Apparatus and system having an integrated inductor

http://ieeexplore.ieee.org/iel5/4242240/4242241/04242377.pdf

Band-Limited Active Damping

Transformator, der umfasst: eine serienparallel gekoppelte Spulentopologie aus Primarspulen (210, 220, 230, 240) und Sekundarspulen (222, 232, 242), die so angeordnet sind, dass sie eine gemeinsame Knotenspannung als einen Mittelwert von N Eingangsknotenspannungen bereitstellen, wobei N eine ganze Zahl groser als zwei ist, und mindestens zwei Sekundarspulen in Serie gekoppelt sind, wobei die serienparallel gekoppelte Spulentopologie umfasst: N Primarspulen (210, 220, 230, 240), wobei jede der Primarspulen elektrisch an jeweils einen von N Eingangsknoten (201-1–201-4) und einen gemeinsamen Ausgangsknoten (250) gekoppelt ist; und N – 1 Sekundarspulen (222, 232, 242), die elektrisch in Serie zwischen einen Eingangsknoten und den gemeinsamen Ausgangsknoten (250) gekoppelt sind, wobei die N – 1 Sekundarspulen (222, 232, 242) so angeordnet sind, dass sie induktiv Energie von N – 1 der Primarspulen (220, 230, 240) koppeln.

Vorrichtung und Verfahren für Mehrphasentransformatoren

An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.

Peter Hazucha

Papers

High-speed comparator with asymmetric frequency response

Apparatus and system having an integrated inductor

Band-Limited Active Damping

Vorrichtung und Verfahren für Mehrphasentransformatoren

Power mangement integrated circuit