As technology scales, variability in transistor performance continues to increase, making transistors less and less reliable. This creates several challenges in building reliable systems, from the unpredictability of delay to increasing leakage current. Finding solutions to these challenges require a concerted effort on the part of all the players in a system design. This article discusses these effects and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.

Designing reliable systems from unreliable components: the challenges of transistor variability and degradation

This paper presents a new multiresonant frequency-adaptive synchronization method for grid-connected power converters that allows estimating not only the positive- and negative-sequence components of the power signal at the fundamental frequency but also other sequence components at other harmonic frequencies. The proposed system is called MSOGI-FLL since it is based on both a harmonic decoupling network consisting of multiple second-order generalized integrators (MSOGIs) and a frequency-locked loop (FLL), which makes the system frequency adaptive. In this paper, the MSOGI-FLL is analyzed for single- and three-phase applications, deducing some key expressions regarding its stability and tuning. Moreover, the performance of the MSOGI-FLL is evaluated by both simulations and experiments to show its capability for detecting different harmonic components in a highly polluted grid scenario.

/pdf/multiresonant-frequency-locked-loop-for-grid-synchronization-1b1w90po2u.pdf

Multiresonant Frequency-Locked Loop for Grid Synchronization of Power Converters Under Distorted Grid Conditions

Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known technique to reduce energy in digital systems, but the effectiveness of DVFS is hampered by slow voltage transitions that occur on the order of tens of microseconds. In addition, the recent trend towards chip-multiprocessors (CMP) executing multi-threaded workloads with heterogeneous behavior motivates the need for per-core DVFS control mechanisms. Voltage regulators that are integrated onto the same chip as the microprocessor core provide the benefit of both nanosecond-scale voltage switching and per-core voltage control. We show that these characteristics provide significant energy-saving opportunities compared to traditional off-chip regulators. However, the implementation of on-chip regulators presents many challenges including regulator efficiency and output voltage transient characteristics, which are significantly impacted by the system-level application of the regulator. In this paper, we describe and model these costs, and perform a comprehensive analysis of a CMP system with on-chip integrated regulators. We conclude that on-chip regulators can significantly improve DVFS effectiveness and lead to overall system energy savings in a CMP, but architects must carefully account for overheads and costs when designing next-generation DVFS systems and algorithms.

/pdf/system-level-analysis-of-fast-per-core-dvfs-using-on-chip-3icz0auash.pdf

System level analysis of fast, per-core DVFS using on-chip switching regulators

Transient errors caused by terrestrial radiation pose a major barrier to robust system design. A system's susceptibility to such errors increases in advanced technologies, making the incorporation of effective protection mechanisms into chip designs essential. A new design paradigm reuses design-for-testability and debug resources to eliminate such errors.

https://www.eng.auburn.edu/~agrawvd/COURSE/E7770_Spr07/READ/01401773.pdf

Robust system design with built-in soft-error resilience

Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.

Characterization of soft errors caused by single event upsets in CMOS processes

Rapidly increasing input current of microprocessors results in rising cost and motherboard real estate occupied by power delivery system. We show that a high-frequency switching DC-DC converter is feasible in 180nm-90nm technology processes for microprocessor power delivery. The current DC-DC converters on microprocessor motherboards are switching at KHz frequencies because of the strict efficiency requirements. We demonstrate a 480MHz DC-DC converter fabricated in a 90nm CMOS process. We also present measurement results on two high-speed CMOS regulation chips to prove high-frequency conversion is a fact.

High-frequency DC-DC conversion : fact or fiction

An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.

Power management integrated circuit

A high-voltage-tolerant 2.4 to 1.2V push-pull linear regulator with 1A output, 288ps response time, and 97.5% current efficiency for biasing integrated DC-to-DC converters is introduced. The regulator occupies 0.03mm2 in 90nm CMOS and achieves 33A/mm2 current density. Digital control with a flash ADC and a digital-to-current converter improve speed-power performance by 3times

A Linear Regulator with Fast Digital Control for Biasing Integrated DC-DC Converters

A system is disclosed. The system includes a load, a voltage regulator circuit coupled to the load a power supply, a load coupled to the power supply to receive one or more voltages from the power supply, and a digital bus, coupled between the power supply and the load. The digital bus transmits power consumption measurements from the load to the power supply and transmits power consumption measurements from the power supply to the load.

Power delivery system

A timing circuit independently controls placement of the positive and negative edges of a periodic signal. This signal may then be used to control a wide variety of integrated circuit applications. The timing circuit includes separate programmable delay lines and a signal processor. Each delay line delays an input clock signal by a different increment of time. The signal processor then generates a timing signal from the clock signal, where the timing signal has a first edge controlled by the first delayed clock signal and a second edge controlled by the second delayed clock signal. The edges may be controlled so that the timing signal assumes different logical values for different amounts of time, thereby customizing the signal to any application. An example of one application includes using the timing signal control switching in a DC-DC converter.

Peter Hazucha

Papers

High-frequency DC-DC conversion : fact or fiction

Power management integrated circuit

A Linear Regulator with Fast Digital Control for Biasing Integrated DC-DC Converters

Power delivery system

Timing circuit for separate positive and negative edge placement in a switching DC-DC converter