As technology scales, variability in transistor performance continues to increase, making transistors less and less reliable. This creates several challenges in building reliable systems, from the unpredictability of delay to increasing leakage current. Finding solutions to these challenges require a concerted effort on the part of all the players in a system design. This article discusses these effects and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.

Designing reliable systems from unreliable components: the challenges of transistor variability and degradation

This paper presents a new multiresonant frequency-adaptive synchronization method for grid-connected power converters that allows estimating not only the positive- and negative-sequence components of the power signal at the fundamental frequency but also other sequence components at other harmonic frequencies. The proposed system is called MSOGI-FLL since it is based on both a harmonic decoupling network consisting of multiple second-order generalized integrators (MSOGIs) and a frequency-locked loop (FLL), which makes the system frequency adaptive. In this paper, the MSOGI-FLL is analyzed for single- and three-phase applications, deducing some key expressions regarding its stability and tuning. Moreover, the performance of the MSOGI-FLL is evaluated by both simulations and experiments to show its capability for detecting different harmonic components in a highly polluted grid scenario.

/pdf/multiresonant-frequency-locked-loop-for-grid-synchronization-1b1w90po2u.pdf

Multiresonant Frequency-Locked Loop for Grid Synchronization of Power Converters Under Distorted Grid Conditions

Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known technique to reduce energy in digital systems, but the effectiveness of DVFS is hampered by slow voltage transitions that occur on the order of tens of microseconds. In addition, the recent trend towards chip-multiprocessors (CMP) executing multi-threaded workloads with heterogeneous behavior motivates the need for per-core DVFS control mechanisms. Voltage regulators that are integrated onto the same chip as the microprocessor core provide the benefit of both nanosecond-scale voltage switching and per-core voltage control. We show that these characteristics provide significant energy-saving opportunities compared to traditional off-chip regulators. However, the implementation of on-chip regulators presents many challenges including regulator efficiency and output voltage transient characteristics, which are significantly impacted by the system-level application of the regulator. In this paper, we describe and model these costs, and perform a comprehensive analysis of a CMP system with on-chip integrated regulators. We conclude that on-chip regulators can significantly improve DVFS effectiveness and lead to overall system energy savings in a CMP, but architects must carefully account for overheads and costs when designing next-generation DVFS systems and algorithms.

/pdf/system-level-analysis-of-fast-per-core-dvfs-using-on-chip-3icz0auash.pdf

System level analysis of fast, per-core DVFS using on-chip switching regulators

Transient errors caused by terrestrial radiation pose a major barrier to robust system design. A system's susceptibility to such errors increases in advanced technologies, making the incorporation of effective protection mechanisms into chip designs essential. A new design paradigm reuses design-for-testability and debug resources to eliminate such errors.

https://www.eng.auburn.edu/~agrawvd/COURSE/E7770_Spr07/READ/01401773.pdf

Robust system design with built-in soft-error resilience

Radiation-induced single event upsets (SEUs) pose a major challenge for the design of memories and logic circuits in high-performance microprocessors in technologies beyond 90nm. Historically, we have considered power-performance-area trade offs. There is a need to include the soft error rate (SER) as another design parameter. In this paper, we present radiation particle interactions with silicon, charge collection effects, soft errors, and their effect on VLSI circuits. We also discuss the impact of SEUs on system reliability. We describe an accelerated measurement of SERs using a high-intensity neutron beam, the characterization of SERs in sequential logic cells, and technology scaling trends. Finally, some directions for future research are given.

Characterization of soft errors caused by single event upsets in CMOS processes

Rapidly increasing input current of microprocessors resulted in rising cost and motherboard real estate occupied by decoupling capacitors and power routing. We show by analysis that an on-die switching DC-DC converter is feasible for future microprocessor power delivery. The DC-DC converter can be fabricated in an existing CMOS process (90nm-180nm) with a back-end thin-film inductor module. We show that 85% efficiency and 10% output voltage droop can be achieved for 4:1, 3:1, and 2:1 conversion ratios, area overhead of 5% and no additional on-die decoupling capacitance. A 4:1 conversion results in 3.4x smaller input current and 6.8x smaller external decoupling.

Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation

This paper presents a technique to selectively engineer sequential or domino nodes in high performance circuits to improve soft error rate (SER) induced by cosmic rays or alpha particles. In 0.18 /spl mu/m process, the SER improvement is as much as 3/spl times/ at the cell-level, 1.8/spl times/ at the block-level and 1.3/spl times/ at the chip-level without any penalty in performance or area, and <3% power penalty. The node selection, hardening and SER quantification steps are fully automated.

Selective node engineering for chip-level soft error rate improvement [in CMOS]

On-chip inductors with 2 levels of magnetic material were integrated into an advanced 130 nm CMOS process to obtain over an order of magnitude (>14times) increase in inductance and Q-factor, significantly greater than prior values of 2.3times for high frequency inductors. The magnetic material is shown to operate at frequencies beyond 6.4 GHz for 1 nH inductors. An amorphous CoZrTa alloy exhibiting high permeability, good high-temperature stability (>250degC), high saturation magnetization, low magnetostriction, high resistivity, minimal hysteretic loss, and compatible with silicon technology was used in combination with magnetic vias and elongated structures that take advantage of the uniaxial magnetic anisotropy

Integrated On-Chip Inductors with Magnetic Films

We measured neutron soft error rate (SER) of hardened and standard latches in a 90 nm dual-Vt CMOS process. The hardened latch demonstrated over 10/spl times/ lower SER at no speed degradation. Energy penalty can be minimal for standard-latch transistor sizes at least twice the minimum size. We analyzed the effects of recovery time and leakage on the SER robustness.

Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process

Integrated DC-DC converters switching above 100MHz dramatically reduce the footprint of the inductors and capacitors while improving droop response. Unfortunately, such converters utilize advanced digital CMOS processes with the maximum input voltage below 2 V. We propose a fully integrated linear regulator that enables doubling of the converter input voltage by properly biasing stacked drivers and bridge transistors. By implementing fast digital control the linear regulator meets the transient current demand of the converter without resorting to off-chip decoupling capacitors. In a 90 nm CMOS process, the 2.4V input, 1.2 V output, linear regulator occupies 0.03 mm2 for a plusmn1 A rating. A 288 ps response time and 97.5% current efficiency result in a 2.84times improvement in speed-power figure of merit over previous work

Peter Hazucha

Papers

Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation

Selective node engineering for chip-level soft error rate improvement [in CMOS]

Integrated On-Chip Inductors with Magnetic Films

Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process

High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters