Wide bandgap semiconductors show superior material properties enabling potential power device operation at higher temperatures, voltages, and switching speeds than current Si technology. As a result, a new generation of power devices is being developed for power converter applications in which traditional Si power devices show limited operation. The use of these new power semiconductor devices will allow both an important improvement in the performance of existing power converters and the development of new power converters, accounting for an increase in the efficiency of the electric energy transformations and a more rational use of the electric energy. At present, SiC and GaN are the more promising semiconductor materials for these new power devices as a consequence of their outstanding properties, commercial availability of starting material, and maturity of their technological processes. This paper presents a review of recent progresses in the development of SiC- and GaN-based power semiconductor devices together with an overall view of the state of the art of this new device generation.

A Survey of Wide Bandgap Power Semiconductor Devices

Wireless power transfer (WPT) using magnetic resonance is the technology which could set human free from the annoying wires. In fact, the WPT adopts the same basic theory which has already been developed for at least 30 years with the term inductive power transfer. WPT technology is developing rapidly in recent years. At kilowatts power level, the transfer distance increases from several millimeters to several hundred millimeters with a grid to load efficiency above 90%. The advances make the WPT very attractive to the electric vehicle (EV) charging applications in both stationary and dynamic charging scenarios. This paper reviewed the technologies in the WPT area applicable to EV wireless charging. By introducing WPT in EVs, the obstacles of charging time, range, and cost can be easily mitigated. Battery technology is no longer relevant in the mass market penetration of EVs. It is hoped that researchers could be encouraged by the state-of-the-art achievements, and push forward the further development of WPT as well as the expansion of EV.

Wireless Power Transfer for Electric Vehicle Applications

DC-link capacitors are an important part in the majority of power electronic converters which contribute to cost, size and failure rate on a considerable scale. From capacitor users' viewpoint, this paper presents a review on the improvement of reliability of dc link in power electronic converters from two aspects: 1) reliability-oriented dc-link design solutions; 2) conditioning monitoring of dc-link capacitors during operation. Failure mechanisms, failure modes and lifetime models of capacitors suitable for the applications are also discussed as a basis to understand the physics-of-failure. This review serves to provide a clear picture of the state-of-the-art research in this area and to identify the corresponding challenges and future research directions for capacitors and their dc-link applications.

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Reliability of Capacitors for DC-Link Applications in Power Electronic Converters—An Overview

Silicon carbide (SiC) power devices have been investigated extensively in the past two decades, and there are many devices commercially available now. Owing to the intrinsic material advantages of SiC over silicon (Si), SiC power devices can operate at higher voltage, higher switching frequency, and higher temperature. This paper reviews the technology progress of SiC power devices and their emerging applications. The design challenges and future trends are summarized at the end of the paper.

https://ieeexplore.ieee.org/ielaam/41/8031005/7815312-aam.pdf

Review of Silicon Carbide Power Devices and Their Applications

Gallium nitride (GaN) power devices are an emerging technology that have only recently become available commercially. This new technology enables the design of converters at higher frequencies and efficiencies than those achievable with conventional Si devices. This paper reviews the characteristics and commercial status of both vertical and lateral GaN power devices, providing the background necessary to understand the significance of these recent developments. In addition, the challenges encountered in GaN-based converter design are considered, such as the consequences of faster switching on gate driver design and board layout. Other issues include the unique reverse conduction behavior, dynamic $R_{\mathrm {{ds}},\mathrm {{on}}}$ , breakdown mechanisms, thermal design, device availability, and reliability qualification. This review will help prepare the reader to effectively design GaN-based converters, as these devices become increasingly available on a commercial scale.

Review of Commercial GaN Power Devices and GaN-Based Converter Design Challenges

Inherent high switching frequency ability makes silicon carbide Metal-Oxide-Semiconductor Field-Effect transistor more sensitive to the parasitics and noise in the circuit. The layout of gate driver has a crucial influence on the parasitics, hereby the propagation delay and rise/fall time of the driving signal which is among the dominant factors to determine the switching performance of power device. In this paper, an automatic layout design based on genetic algorithm for gate driver is developed. Detailed description of the gate driver layout design is given. Experimental results verified the effectiveness of the design procedure. The speed and validity of the approach make it a valuable tool, and it can be extended to power circuit design, even power converter design easily.

Automatic layout design for gate driver of SiC MOSFET

This paper is devoted to study the thermal stress of a novel bondline based on Cu@Sn preform and analyze the failure mode of solder joint and SiC module. The 2D simplified model of chip-DBC substrate was created, according to the stress evaluating equations, the interfacial peel stress of chip-solder and solder-substrate was numerically calculated, and the stress distribution was imitated by ANSYS software, the results revealed that the peel stress mostly concentrated on the corners of the joint, and decreased with increased joint thickness, the peel stress could be negligible when joint thickness was greater than 50μm. Compared to the high-lead alloy system and sinter nano-silver system, the three-dimensional network structure bondline based on Cu@Sn possessed the minimum tensile stress (3MPa) and compress stress (15MPa). The multi-layer model of SiC module was built to study the influence of bondline layer thickness variation on module reliability, the result indicated that the chip stress was little dependent on the soldering layer thick, and the module stress bonded by the novel bondline was slightly larger than that of high lead system and sintered Ag system. The favorable thick bondline based on Cu@Sn preform was experimentally proved to have better mechanical strength. Shearing strength of the joint at room temperature was up to 49.5MPa, thermal cycling from -70 to 200 for 100cycles, there was no crack available on the joint, due to the pore volume got bigger, shear strength got smaller, the bondline could still function well for mechanical support.

Investigation on thermal stress of bondline based on Cu@Sn preform at high temperature application

This paper presents a novel method for gate capacitances extraction of Insulated Gate Bipolar Transistor (IGBT). Gate capacitances are critical for IGBT physical models with accurate turn-on/off transient characteristics. The model is developed and expanded based on the conventional IGBT physical model, and the developed method can be obtained by several simple experiments. The presented method was verified by both IGBT datasheet and professional measurements, and can be used for gate capacitances extraction of Power Metal-Oxide- Semiconductor Field Effect Transistor (MOSFET) and Integrated Gate Commutated Thyristor (IGCT).

http://ieeexplore.ieee.org/iel7/6927584/6940609/06940948.pdf

A novel method of gate capacitances extraction for IGBT physical models

The microstructure and properties of Cu@Cu3Sn@Cu6Sn5three-dimensional network bonding interconnections based on Cu@Sn preform was investigated. No through holes were observed at the bulk in as-reflowed, aged and temperature cycling bondlines. Microstructure evolution and phase transformation during thermal treatment test were studied, the shear strength of three-dimensional network bondlines for as-reflowed and thermal treating samples were compared and analyzed. The phase composition of as-reflowed interconnects was Cu/Cu6Sn5 and transformed to Cu/Cu3Sn/Cu6Sn5 after thermal treatment. Different failure modes of as-reflowed, aged and temperature cycling test were found in three-dimensional network structure bondline. The average shear strength of the as-reflowed and the thermal treatment bonding interconnections are 49.5 MPa and 24.9 MPa, respectively, and crack initiated and propagated that perpendicular to substrate during the aging test. The fracture surfaces of the temperature treatment bonding interconnections after shearing test were characterized in detail. The results show that the Cu3Sn phases in Cu@Cu3Sn@Cu6Sn5 three-dimensional network structure affected its strength and fracture mode. The Cu-rich substrate side at the fracture surfaces is always regular while the bulk phases are often accompanied by shear bands and dimples.

Microstructure evolution and properties evaluation of a novel bondline based on Cu@Sn Preform during temperature treatment

The invention discloses an insulated gate bipolar transistor (IGBT) model for the electromagnetic interference simulation analysis. The IGBT model comprises a positive conduction part model (11) and an anti-parallel diode part model (12). The two models together form a branch formed through the serial connection of a resistor Rc35 and a capacitor C35. The positive conduction part model (11) comprises four branches that are connected in parallel, wherein the anode of a first ideal diode Dv is connected with the collector of an IGBT, and the other end of a resistor Rv is connected with an emitter of the IGBT. The anti-parallel diode part model (12) comprises three branches that are connected in parallel. The cathode of a second ideal diode Dd is connected with the collector of the IGBT. The anode of the second ideal diode Dd is connected with the emitter of the IGBT. According to the technical scheme of the invention, the branch formed through the serial connection of the resistor Rc35 and the capacitor C35 is composed of the fourth branch of the positive conduction part model of the IGBT and the third branch of the anti-parallel diode part model of the IGBT.

Puqi Ning

Papers

Automatic layout design for gate driver of SiC MOSFET

Investigation on thermal stress of bondline based on Cu@Sn preform at high temperature application

A novel method of gate capacitances extraction for IGBT physical models

Microstructure evolution and properties evaluation of a novel bondline based on Cu@Sn Preform during temperature treatment

Insulated gate bipolar transistor (IGBT) model for electromagnetic interference simulation analysis