Printable oxide transistors have emerged as important optoelectronic synaptic devices to emulate the human visual cognitive system by integrating both photo‐sensing and visual perception functions. However, the inferior electrical performance and low pixel density of printed oxide synaptic transistors impede their implementation of complex neuromorphic computing. Herein, a printable all‐oxide optoelectronic synaptic transistor array based on a modified coffee‐ring structure of indium tin oxide (ITO) is reported. The extraordinary structural design endows the printed ITO transistors with high device uniformity, outstanding electrical performance, and superior process efficiency. Furthermore, a 10 × 12 coffee‐ring structure optoelectronic synaptic transistor array with a high spatial resolution (142 dpi) exhibits durable visual detection and memory behaviors. Meanwhile, an artificial neural network based on the coffee‐ring structure synaptic transistors exhibits high accuracy in the recognition rate. These results promise the efficiency of the exceptional printing strategy in developing advanced optoelectronic synaptic transistors for artificial visual systems.

Printable Coffee‐Ring Structures for Highly Uniform All‐Oxide Optoelectronic Synaptic Transistors

In this study, we applied microwave annealing (MWA) to fabricate amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) without thermal damage to flexible polyimide (PI) substrates. Microwave energy is highly efficient for selective heating of materials when compared to conventional thermal annealing (CTA). We applied MWA and CTA to a-IGZO TFTs on PI substrate to evaluate the thermal damage to the substrates. While the PI substrate did not suffer thermal damage even at a high power in MWA, it suffered severe damage at high temperatures in CTA. Moreover, a-IGZO TFTs were prepared by MWA at 600 W for 2 min, whereas the same process using CTA required 30 min at a temperature of 300 °C, which is a maximum process condition in CTA without thermal damage to the PI substrate. Hence, MWA TFTs have superior electrical performance when compared to CTA TFTs, because traps/defects are effectively eliminated. Through instability evaluation, it was found that MWA TFTs were more stable than CTA TFTs against gate bias stress at various temperatures. Moreover, an MWA TFT-constructed resistive load inverter exhibited better static and dynamic characteristics than the CTA TFT-constructed one. Therefore, MWA is a promising thermal process with efficient energy conversion that allows the fabrication of high-performance electronic devices.

https://www.mdpi.com/1996-1944/14/10/2630/pdf

Thermal Damage-Free Microwave Annealing with Efficient Energy Conversion for Fabricating of High-Performance a-IGZO Thin-Film Transistors on Flexible Substrates.

Various annealing atmospheres were employed during our unique thermal-diffusion type Ga-doping process to investigate the surface, structural, optical, and electrical properties of Ga-doped zinc oxide (ZnO) nanoparticle (NP) layers. ZnO NPs were synthesized using an arc-discharge-mediated gas evaporation method, followed by Ga-doping under open-air, N2, O2, wet, and dry air atmospheric conditions at 800 °C to obtain the low resistive spray-coated NP layers. The I–V results revealed that the Ga-doped ZnO NP layer successfully reduced the sheet resistance in the open air (8.0 × 102 Ω/sq) and wet air atmosphere (8.8 × 102 Ω/sq) compared with un-doped ZnO (4.6 × 106 Ω/sq). Humidity plays a key role in the successful improvement of sheet resistance during Ga-doping. X-ray diffraction patterns demonstrated hexagonal wurtzite structures with increased crystallite sizes of 103 nm and 88 nm after doping in open air and wet air atmospheres, respectively. The red-shift of UV intensity indicates successful Ga-doping, and the atmospheric effects were confirmed through the analysis of the defect spectrum. Improved electrical conductivity was also confirmed using the thin-film-transistor-based structure. The current controllability by applying the gate electric-field was also confirmed, indicating the possibility of transistor channel application using the obtained ZnO NP layers. 

/pdf/effects-of-ambience-on-thermal-diffusion-type-ga-doping-2k0oly0p.pdf

Effects of Ambience on Thermal-Diffusion Type Ga-doping Process for ZnO Nanoparticles

We examine low-temperature fabricated InSnO/ZnO (ITO/ZnO) heterojunction thin-film transistors (TFTs) with high mobility and excellent stability. The effects of ITO thickness (0, 2, 4, 6, and 8 nm) on performance of the ITO/ZnO TFTs are studied. For the devices with a 6-nm ITO layer, a field-effect mobility (<inline-formula> <tex-math notation="LaTeX">$\mu _{\mathrm{FE}}$ </tex-math></inline-formula>) of 55.50 cm<sup>2</sup>/Vs, a subthreshold swing (SS) of 113.22 mV/decade, a turn-on voltage (<inline-formula> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ON}}$ </tex-math></inline-formula>) of −3 V, and an on/off current ratio (<inline-formula> <tex-math notation="LaTeX">$\text{I}_{\mathrm{ON}}/\text{I}_{\mathrm{OFF}}$ </tex-math></inline-formula>) over 10<sup>7</sup> are obtained. Besides, the devices demonstrate excellent stability with a threshold voltage shift of 0.68 and −0.25 V under the positive and negative gate-bias stress, respectively. Operation mode of the ITO/ZnO TFTs is analyzed. The results show that potential well at ITO/ZnO heterointerface forms electronic accumulation, which is beneficial to improve the <inline-formula> <tex-math notation="LaTeX">$\mu _{\mathrm{FE}}$ </tex-math></inline-formula> of the ITO/ZnO TFTs. Our work promotes applications of the oxide TFTs to back-end-of-line (BEOL) circuits.

Back-End-of-Line Compatible InSnO/ZnO Heterojunction Thin-Film Transistors With High Mobility and Excellent Stability

Transparent conductive oxides (TCO) have been extensively investigated as channel materials for thin-film transistors (TFTs). In this study, highly transparent and conductive InSnO (ITO) and ZnO films were deposited, and their material properties were studied in detail. Meanwhile, we fabricated ZnO/ITO heterojunction TFTs, and explored the effects of channel structures on the hump characteristics of ZnO/ITO TFTs. We found that Vhump–VON was negatively correlated with the thickness of the bottom ZnO layer (10, 20, 30, and 40 nm), while it was positively correlated with the thickness of the top ITO layer (3, 5, 7, and 9 nm), where Vhump is the gate voltage corresponding to the occurrence of the hump and VON is the turn-on voltage. The results demonstrated that carrier transport forms dual current paths through both the ZnO and ITO layers, synthetically determining the hump characteristics of the ZnO/ITO TFTs. Notably, the hump was effectively eliminated by reducing the ITO thickness to no more than 5 nm. Furthermore, the hump characteristics of the ZnO/ITO TFTs under positive gate-bias stress (PBS) were examined. This work broadens the practical application of TCO and provides a promising method for solving the hump phenomenon of oxide TFTs.

/pdf/structural-engineering-effects-on-hump-characteristics-of-j80dwhqs.pdf

Structural Engineering Effects on Hump Characteristics of ZnO/InSnO Heterojunction Thin-Film Transistors

InSnO (ITO) thin-film transistors (TFTs) attract much attention in fields of displays and low-cost integrated circuits (IC). In the present work, we demonstrate the high-performance, robust ITO TFTs that fabricated at process temperature no higher than 100 °C. The influences of channel thickness (tITO, respectively, 6, 9, 12, and 15 nm) on device performance and positive bias stress (PBS) stability of the ITO TFTs are examined. We found that content of oxygen defects positively correlates with tITO, leading to increases of both trap states as well as carrier concentration and synthetically determining electrical properties of the ITO TFTs. Interestingly, the ITO TFTs with a tITO of 9 nm exhibit the best performance and PBS stability, and typical electrical properties include a field-effect mobility (µFE) of 37.69 cm2/Vs, a Von of −2.3 V, a SS of 167.49 mV/decade, and an on–off current ratio over 107. This work paves the way for practical application of the ITO TFTs.

Effects of Channel Thickness on Electrical Performance and Stability of High-Performance InSnO Thin-Film Transistors

In the present work, we testify a strategy to achieve high-performance ZnO thin film transistors (TFTs) on a flexible PET substrate at a maximum process temperature no more than 100 °C. Interestingly, the ZnO TFTs exhibit superior electrical properties, including a field-effect mobility of 14.32 cm2V−1s−1, a sub-threshold swing of 0.21 V/decade, and an on-to-off current ratio of $3.03\times 10^{7}$ . Also, ideal uniformity, hysteresis property, contact resistance, and stability are achieved. Threshold voltage shift ( $\Delta \text{V}_{\mathrm{ TH}}$ ) under positive and negative bias stress are 0.17 and −0.18 V, respectively. Moreover, the ZnO TFTs manifest good mechanical performance at a bending radius of 10 mm. We expect that our findings propel practical application of the oxide TFTs in flexible electronics.

/pdf/high-performance-zno-thin-film-transistors-on-flexible-pet-1zl99j44hm.pdf

High-Performance ZnO Thin-Film Transistors on Flexible PET Substrates With a Maximum Process Temperature of 100 °C

High-performance ZnO thin film transistors (TFTs) are fabricated by atomic layer deposition (ALD). The effects of the deposition temperature of ZnO active layer (80, 100, 120, and 140°C) on performance of TFTs are investigated. Devices with ZnO active layer deposited at 120°C exhibit the best performance, such as a field-effect mobility of 31.79 cm2V−1s−1, a sub-threshold slope of 181 mV/decade, an on/off state current ratio over 109. Besides, the devices show −0.22 and 0.19 V threshold voltage shift under positive and negative gate-bias stress.

Qi Li

Papers

Effects of Channel Thickness on Electrical Performance and Stability of High-Performance InSnO Thin-Film Transistors

High-Performance ZnO Thin-Film Transistors on Flexible PET Substrates With a Maximum Process Temperature of 100 °C

Back-End-of-Line Compatible InSnO/ZnO Heterojunction Thin-Film Transistors With High Mobility and Excellent Stability

Structural Engineering Effects on Hump Characteristics of ZnO/InSnO Heterojunction Thin-Film Transistors

High-performance ZnO Thin-Film Transistors Prepared by Atomic Layer Deposition at Low Temperature