X
Xing Zhang
Researcher at Peking University
Publications - 589
Citations - 3594
Xing Zhang is an academic researcher from Peking University. The author has contributed to research in topics: MOSFET & Thin-film transistor. The author has an hindex of 23, co-authored 559 publications receiving 3062 citations.
Papers
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Journal ArticleDOI
A Physics-Based Compact Model of Metal-Oxide-Based RRAM DC and AC Operations
Peng Huang,Xiaoyan Liu,Bing Chen,Haitong Li,Yi Jiao Wang,Yexin Deng,Kang Liang Wei,Lang Zeng,Bin Gao,Gang Du,Xing Zhang,Jinfeng Kang +11 more
TL;DR: In this article, a physics-based compact model of metal-oxide-based resistive-switching random access memory (RRAM) cell under dc and ac operation modes is presented.
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Analog/RF Performance of Si Nanowire MOSFETs and the Impact of Process Variation
Runsheng Wang,Jing Zhuge,Ru Huang,Yu Tian,Han Xiao,Liangliang Zhang,Li Chen,Xing Zhang,Yangyuan Wang +8 more
TL;DR: In this paper, the analog/RF performance of Si nanowire transistors (SNWTs) and the impact of process variation are investigated for the first time, and the results indicate that SNWTs exhibit superior intrinsic RF scaling capability and are suitable for low-power analog and RF applications.
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Synthesis and characterization of single-crystalline α-Fe2O3 nanoleaves
TL;DR: In this paper, a single crystalline α-Fe 2 O 3 nanoleaves were synthesized by oxygenating pure iron by carefully controlling the reacting conditions, including atmosphere, temperature, and time.
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Experimental Investigations on Carrier Transport in Si Nanowire Transistors: Ballistic Efficiency and Apparent Mobility
Runsheng Wang,Hongwei Liu,Ru Huang,Jing Zhuge,Liangliang Zhang,Dong-Won Kim,Xing Zhang,Donggun Park,Yangyuan Wang +8 more
TL;DR: In this article, experimental studies on the carrier transport in gate-all-around (GAA) silicon nanowire transistors (SNWTs) are reported, demonstrating their great potential as an alternative device structure for near-ballistic transport from top-down approach.
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Layout Design Correlated With Self-Heating Effect in Stacked Nanosheet Transistors
TL;DR: In this article, the authors investigate the self-heating of horizontally stacked three-layer gate-all-around (GAA) transistors by 3-D finite-element modeling (FEM) simulation.