Showing papers by "Qianqian Huang published in 2011"

Self-depleted T-gate Schottky barrier tunneling FET with low average subthreshold slope and high I ON /I OFF by gate configuration and barrier modulation

Abstract: In this paper, a novel silicon-based T-gate Schottky barrier tunneling FET (TSB-TFET) is proposed and experimentally demonstrated. With enhanced electric field at source side through gate configuration for steeper subthreshold slope (SS), the device with self-depleted structure can effectively suppress the leakage current and simultaneously achieve the dominant Schottky barrier tunneling current for high ON-current without area penalty, which can alleviate the problems in silicon TFET. In addition, the proposed TSB-TFET can have comparable DIBL effect and reduced gate-to-drain capacitance compared with traditional TFET. Further device optimization is experimentally achieved by extended multi-finger gate configuration of the same footprint and barrier modulation by dopant segregation Schottky technology. With compatible bulk CMOS technology, the fabricated device can achieve steep SS over almost 5 decades of current, as well as high I ON /I OFF ratio (∼107). The proposed device with high compatibility is very promising for future low power system applications.

Schottky barrier impact-ionization metal-oxide-semiconductor device with reduced operating voltage

Abstract: In this letter, a Schottky barrier impact-ionization metal-oxide-semiconductor (SB-IMOS) device with reduced operating voltage is proposed and investigated. By introducing the silicide source and combining impact ionization with Schottky barrier tunneling, source parasitical resistance can be extremely reduced and the device performance can be improved. The device is optimized with Schottky barrier height variation additionally. Both SB-IMOS and conventional impact-ionization metal-oxide-semiconductor devices were fabricated using the standard complementary metal-oxide-semiconductor technology. SB-IMOS exhibits a 33% lower operating voltage, 43% lower threshold voltage, and improvement of ON current by 2 orders of magnitude while maintaining steep subthreshold swing of 10.2 mV/dec.

Tunneling current amplification transistor

Abstract: The present invention discloses a tunneling current amplification transistor, which relates to an area of field effect transistor logic devices in CMOS ultra large scale semiconductor integrated circuits (ULSI). The tunneling current amplification transistor includes a semiconductor substrate, a gate dielectric layer, an emitter, a drain, a floating tunneling base and a control gate, wherein the drain, the floating tunneling base and the control gate forms a conventional TFET structure, and a doping type of the emitter is opposite to that of the floating tunneling base. A position of the emitter is at the other side of the floating tunneling base with respect to the drain. A type of the semiconductor between the emitter and the floating tunneling base is the same as that of the floating tunneling base. As compared with the conventional TFET, the tunneling current amplification transistor of the present invention can increase the on-current of the device effectively and increase the driving capability of the device.

Tunneling field effect transistor with T-shaped grid structure and low power consumption

Abstract: The invention provides a tunneling field effect transistor (TFET) with a T-shaped grid structure and low power consumption, and belongs to the field of field effect transistor logic devices and circuits in complementary metal oxide semiconductor (CMOS) ultra large scale integrated circuits (ULSI). The TFET comprises a source electrode, a drain electrode and a control grid, wherein the control grid extends toward the end of the source electrode to form a T shape; the T-shaped control grid consists of an extending grid region and the original control grid region; and an active region covered below the extending grid region is a channel region and is made of a substrate material. By using the T-shaped grid structure, the source region of the TFET encircles a channel, so that the conduction current of a device is improved. Compared with the conventional planar TFET, the TFET can achieve higher conduction current and steeper subthreshold slope under the same process conditions and the samesize of the active region.

Low-power consumption tunneling field effect transistor (TFET) of fork-structure grid structure

Abstract: The invention provides a low-power consumption tunneling field effect transistor (TFET), belonging to the field of a field effect transistor logic device and a circuit of CMOS (complementary metal oxide semiconductors) ultra large scale integrated circuit (ULSI). The TFET provided by the invention comprises a source, a drain and a control grid, wherein the control grid extends towards a source electrode end into a fork structure, and the fork-structure control grid is composed of an extended grid region and an original control grid region; and the active region which is covered below the extended grid region is similarly a channel region and is made of a substrate material. According to the invention, the channel is enclosed by the source region of the TFET, and the conduction current of the device is improved; and compared with the existing panel TFET, the TFET has provided by the invention has the advantage that under the conditions of the same technology and the same active region size, higher conduction current and a steep subthreshold gradient can be obtained.

Tunneling field effect transistor and preparation method thereof

Abstract: The invention discloses a tunneling field effect transistor and a preparation method thereof. The transistor comprises: a semiconductor substrate, a first channel region and a second channel region, a first gate stack zone, a second gate stack zone, a first source zone, a leakage zone, a second source zone a third insulating layer and a source electrode S, wherein the first conducting layer in the first gate stack zone is connected with the second conducting layer of the second gate stack outside the channel region to form a interdigital grid; the electrodes of the first source zone and second source zone, the drain electrode in the leakage zone and the gate electrode G on the interdigital grid are formed in the third insulating layer. According to the invention, the work current of the tunneling field effect device provided in the invention is a tunneling current and the work current is a current of an MOS (Metal-Oxide-Semiconductor) field effect transistor. The driving current is substantially improved. Meanwhile, the manufacture technology is compatible with the tradition technology and the area is saved, because the interdigital structure is adopted and the first source zone plays a role in substrate lead-out.

Field effect transistor of hybrid conduction mechanism

Abstract: The invention discloses a field effect transistor with a hybrid conduction mechanism, belonging to the field of field effect transistor logic devices in CMOS (Complementary Metal-Oxide-Semiconductor) ultra-large-scale integration (ULSI) circuits. The field effect transistor of the hybrid conduction mechanism comprises a source electrode, a drain electrode, a channel region and a control grid, wherein the source electrode comprises a tunneling source electrode and a diffusion source electrode. For an N-type device, a source region comprises a P-type tunneling source electrode which is shallower in junction depth and an N-type diffusion source electrode which is deeper in junction depth. For a P-type device, a source region comprises an N-type shallow tunneling source electrode and a P-typedeep diffusion source electrode. The tunneling source electrode and the diffusion source electrode are subjected to potential lead-out on the source electrode at the same time; the doping type of thedrain electrode is same as that of the diffusion source electrode at the source end, and the doping type of a substrate is same as that of the tunneling source electrode. Compared with the traditional TFET (Tunneling Field Effect Transistor), the field effect transistor disclosed by the invention can be used for effectively increasing the conduction current of a device and improving the driving capability of the device.

Flash memory and fabrication method and operation method for the same

Abstract: The present invention discloses a flash memory and the fabrication method and the operation method for the same. The flash memory comprises two memory cells of vertical channels, wherein a lightly-doped N type (or P type) silicon is used as a substrate; a P+ region (or an N+ region) is provided on each of the both ends of the silicon surface, and two channel regions perpendicular to the surface are provided therebetween; an N+ region (or a P+ region) shared by two channels is provided over the channels; a tunneling oxide layer, a polysilicon floating gate, a block oxide layer and a polysilicon control gate are provided sequentially on the outer sides of each channel from inside to outside; and the polysilicon floating gate and the polysilicon control gate are isolated from the P+ region by a sidewall oxide layer. The whole device is a two-bit TFET type flash memory with vertical channels which has better compatibility with prior-art standard CMOS process. As compared with a conventional MOSFET-based flash memory, the flash memory according to the present invention possesses various advantages such as high programming efficiency, low power consumption, effective inhibition of punch-through effect, and high density, etc.

A Novel High Programming Efficiency and Highly Scalable Flash Memory Cell Based on Tunneling FET (TFET)

Abstract: A novel flash memory cell based on Tunneling Field Effect Transistor (TFET) is proposed and investigated in this paper. Based on the TFET structure, the proposed novel flash memory cell shows high programming efficiency, low power consumption, and good punch-through immunity. Unlike traditional NOR Flash cell which adopts the channel hot carrier (CHE) injection near drain side for programming operation, the TFET flash memory cell utilizes hot electrons injection introduced by band-to-band tunneling near source side for programming, which can achieve 3 orders higher programming efficiency due to greatly alleviated competition between the vertical electric field and lateral electric field. Moreover, the programming leakage current is 2 orders lower due to the high punch-through immunity for TFET structure. The obtained results and theoretical analysis demonstrate that the newly proposed flash cell can be a potential candidate for low power, and high density NOR-type flash applications.

Multiple source MOS transistor with impurity segregation and production method thereof

Abstract: The invention provides a multiple source MOS (metal oxide semiconductor) transistor with impurity segregation and a production method thereof. The multiple source MOS transistor comprises a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region; one end of a control gate extends towards the highly-doped sourceregion to form a T shape; the extended gate region is used as an extension gate; an original control gate region is a main gate; the highly-doped source region is formed by highly doping a semiconductor and is positioned on two sides of the extension gate along the width direction of the source region; and one side of the highly-doped region, which is away from the channel direction, is connectedwith a Schottky source region with impurity segregation. Compared with the present MOSFET (metal-oxide-semiconductor field-effect transistor), under the same process condition and the same size of the active region, higher conducting current, lower leakage current and steeper sub-threshold slope can be obtained.

Tunneling field effect transistor with double-gate structure and preparing method thereof

Abstract: The invention discloses a tunneling field effect transistor and a preparing method thereof The transistor disclosed by the invention is in a double-gate structure comprising an outer gate and an inner gate, an annular channel region which is perpendicular to a semiconductor substrate, an annular source region and an annular drain region, wherein the inner gate includes an inner gate conductive layer and an inner gate medium layer; and the outer gate includes an outer gate conductive layer and an outer gate medium layer According to the tunneling field effect transistor with the double-gate structure disclosed by the invention, the double-gate structure has the advantages of strong gate control capability, capability of inhibiting short channel effect and sub-threshold character degeneration, and capability of increasing drive capability of devices; the tunneling field effect transistor employing the double-gate structure is increased in performance, specifically, the drive capability of the tunneling field effect transistor is stronger and sub-threshold gradient of the tunneling field effect transistor is better

Deep energy level impurity ionizing collision transistor

Abstract: The invention provides a deep energy level impurity ionizing collision transistor belonging to the fields of field effect transistor logic devices and circuits in a CMOS (Complementary Metal Oxide Semiconductor) ultra large scale integrated circuit (ULSI). The transistor comprises the same N-type or P-type doped source electrode and drain electrode, a control gate and a high-resistance drift region, wherein the drift region comprises deep energy level impurities which can ionize carriers under a high field; leakage current of the device can be reduced by the high-resistance drift region in an off state; and a large amount of carriers can be instantly provided when the device is in an on state, so that the on of the device is promoted. Compared with the conventional low-power-consumption device TFET (Tunneling Field Effect Transistor), since drift diffusion current is adopted, larger on current and steeper sub-threshold frequency can be achieved. Compared with the conventional low-power-consumption device IMOS (Ion Implanted Metal Oxide Semiconductor), since a critical electric field of deep energy level impurity ionization is far lower than an avalanche critical electric field, the reliability of the device can be enhanced while working points of the device are greatly reduced.

Comb-shaped gate composite source MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof

Abstract: The invention provides a composite source MOS (Metal Oxide Semiconductor) transistor with schottky barrier and comb-shaped gate structures and a manufacturing method thereof. The composite source MOS transistor comprises a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a high doped source region and a high doped drain region, wherein one side far away from the channel direction of the high doped source region is connected with a schottky source region; one end of a control gate extends towards the high doped source region; the extended gate region is an extension gate shaped like a comb; the original control gate region is a main gate; the active region covered by the extension gate is likewise a channel region with the substrate material; the high doped source region is formed by the high doping of semiconductor and is located on the two sides of each comb of the extension gate; and a schottky junction is formed at the channel under the schottky source region and the extension gate. Compared with the traditional MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), the composite source MOS transistor can obtain a higher conduction current, a lower leakage current and a steeper subthreshold slope under a same technological condition and a same active region size.

A novel flash memory cell and design optimization for high density and low power application

Abstract: A novel flash memory cell based on Tunneling Field Effect Transistor (TFET) is investigated via 2-D device simulation in this paper. The proposed flash memory cell shows improved program/erase speed, increased programming efficiency and super punch-through immunity as the cell gate length scaled from 180nm to 45nm, which indicates that this new structure is with strong scalability. Furthermore, cell design consideration i.e. ambipolar suppression for the TFET-based flash cell are also investigated and discussed.

Resistive Field Effect Transistor Having an Ultra-Steep Subthreshold Slope and Method for Fabricating the Same

Abstract: The invention discloses a resistive field effect transistor (ReFET) having an ultra-steep subthreshold slope, which relates to a field of field-effect-transistor logic device and circuit in CMOS ultra-large-scale-integrated circuit (ULSI) The resistive field effect transistor comprises a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a doped source region and a doped drain region, wherein the control gate is configured to adopt a stacked gate structure in which a bottom layer or a bottom electrode layer, a middle layer or a resistive material layer, and a top layer or a top electrode layer are sequentially formed Compared with the existing methods for breaking the conventional subthreshold slope limititation, the device of the invention has a larger on-current, a lower operation voltage, and a better subthreshold feature

MOS Transistor Having Combined-Source Structure With Low Power Consumption and Method for Fabricating the Same

Abstract: The present invention discloses a MOS transistor having a combined-source structure with low power consumption, which relates to a field of field effect transistor logic devices and circuits in CMOS ultra-large-scaled integrated circuits. The MOS transistor includes a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a Schottky source region, a highly-doped source region and a highly-doped drain region. An end of the control gate extends to the highly-doped source region to form a T shape, wherein the extending region of the control gate is an extending gate and the remaining region of the control gate is a main gate. The active region covered by the extending gate is a channel region, and material thereof is the substrate material. A Schottky junction is formed between the Schottky source region and the channel under the extending gate. The combined-source structure according to the invention combines a Schottky barrier and a T-shaped gate, improves the performance of the device, and the fabrication method thereof is simple. Thus, a higher turn-on current, a lower leakage current, and a steeper subthreshold slope can be obtained, and the present application can be applied in the field of low power consumption and have a higher practical value.

Combined-source Mos Transistor with Comb-shaped Gate, and Method for Manufacturing the Same

Abstract: The present invention discloses a combined-source MOS transistor with a Schottky Barrier and a comb-shaped gate structure, and a method for manufacturing the same. The combined-source MOS transistor includes: a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a highly-doped source region and a highly-doped drain region, wherein a Schottky source region is connected to a side of the highly-doped source region which is far from a channel, one end of the control gate extends to the highly-doped source region, the extended gate region is an extension gate in a form of a comb-shaped and the original control gate region is a main gate; an active region covered by the extension gate is also a channel region, and is a substrate material; the highly-doped source region which is formed by highly doping is located on both sides of each comb finger of the extension gate; and a Schottky junction is formed at a location where the Schottky source region and the channel under the extension gate are located. As compared with an existing MOSFET, in the invention, a higher turn-on current, a lower leakage current and a steeper subthreshold slope may be obtained under the same process condition and the same active region size.

Resistance-variable field effect transistor with ultra-steep sub-threshold slope and production method thereof

Abstract: The invention provides a resistance-variable field effect transistor with an ultra-steep sub-threshold slope and belongs to the fields of field effect transistor logic devices and circuits in CMOS (complementary metal-oxide-semiconductor) ultra large scale integration (ULSI) circuits. The resistance-variable field effect transistor comprises a control gate electrode layer, a gate dielectric layer, a semiconductor substrate, a source doping region and a drain doping region; and the control gate is in a gate stacked structure, sequentially including a bottom electrode layer as a bottom layer, a resistance variable material layer as an intermediate layer and a top electrode layer as a top layer. Compared with the present method making breakthrough on the limit of the sub-threshold slope, the resistance-variable field effect transistor has heavier conducting current, lower work voltage and better sub-threshold characteristic.

Low-power consumption tunneling field-effect transistor with finger-shaped gate structure

Abstract: The present invention discloses a low-power consumption tunnelling field-effect transistor (TFET). The TFET according to the invention includes a source, a drain and a control gate, wherein the control gate extends towards the source to form a finger-type control gate, which includes an extended gate region and an original control gate region, and an active region covered by the extended gate region is also an channel region and is made of the substrate material. The invention employs a finger-shaped gate structure, and the source region of the TFET surrounds the channel so that the on-state current of the device is improved. In comparison with the conventional planar TFET, a higher on-state current and a steeper subthreshold slope may be obtained under the same process conditions and with the same active region size.

Cooling structure of chip

Abstract: The invention provides a cooling structure of a chip, belonging to the field of microelectronics. The cooling structure comprises a P-type superlattice layer and an N-type superlattice layer which are formed on the upper surface of the chip through oxide isolation; a P-type superlattice and an N-type superlattice are isolated by silicon dioxide; the P-type superlattice is electrically connected with a metal layer of the chip through a touch hole, wherein the metal layer of the chip is connected with a low-potential power supply, and meanwhile, a metal layer formed above the P-type superlattice is connected with an external power supply; the N-type superlattice is electrically connected with a metal layer of the chip through a contact hole, wherein the metal layer of the chip is connected with a high-potential power supply, and meanwhile, a metal layer formed above the N-type superlattice is connected with an external power supply; and the potential of the external power supply connected with the P-type superlattice is lower than that of the external power supply connected with the N-type superlattice. By utilizing the characteristics of low thermal conductance and similar phonon localization behaviors of the superlattices, the heat of the chip can be radiated, and meanwhile, the heat from the surrounding environment can be inhibited to transfer to the chip.

CMOS device for reducing radiation-induced charge collection and method for fabricating the same

Abstract: A CMOS device for reducing a radiation-induced charge collection and a method for fabricating the same. In the CMOS device, a heavily doped charge collection-suppressed region is disposed directly under the source region and the drain region. The region has a doping type opposite that of the source region and the drain region, and has a doping concentration not less than that of the source region and the drain region. The charge collection-suppressed region has a lateral part slightly less than or equal to that of the source region and the drain region, and has a lateral range toward to the channel not exceed the edges of the source region and the drain region. The CMOS device may greatly reduce a range of the funnel that appears under the action of a single particle, so that charges collected instantaneously under a force of an electric field may be reduced.

Heat dissipation structure of chip

Abstract: A heat dissipation structure of a chip in the field of microelectronics is provided. The heat dissipation structure includes a P-type superlattice layer and an N-type superlattice layer formed over an upper surface of the chip by oxidation isolation. The P-type superlattice and the N-type superlattice are isolated by silicon oxide. Through a contact hole the P-type superlattice is electrically connected to a metal layer that is applied with a low potential in the chip, and a metal layer to be connected with an external power source is formed over the P-type superlattice. Through a contact hole the N-type superlattice is electrically connected to a metal layer that is applied with a high-potential power source in the chip, and a metal layer to be connected with an external power source is formed over the N-type superlattice. The potential of the external power source connected with the P-type superlattice is lower than that of the external power source connected with the N-type superlattice. The present invention can achieve heat dissipation of the chip and meanwhile prevent the ambient heat from transferring into the chip, by using the feature that the superlattice has a low thermal conductivity and phonon-localization-like behavior.

Chip cooling structure

Abstract: Provided is a chip cooling structure, comprising a layer of p-type and n-type superlattice (106, and 105) formed on the upper surface of a chip via oxidation and insulation. The p-type superlattice (106) and the n-type superlattice (105) are insulated therebetween by silicon dioxide (107), a p-type superlattice (106) is electrically connected to a low potential conducting metallic layer (102) of the chip via a contact hole (104), and a metallic layer connecting to an external power source (108) is formed above the p-type superlattice (106). The n-type superlattice (105) is electrically connected to a high potential supply metallic layer (103) of the chip via the contact hole (104), and a metallic layer connecting to an external power source (109) is formed above the n-type superlattice (105). The potential of the external power source (108) connected to the p-type superlattice (106) is lower than that of the external power source (109) connected to the n-type superlattice (105). Employment of the superlattice characteristics of low thermal conductivity and phonon localization-like behavior cools the chip while inhibiting a transfer of heat from the surrounding environment to the chip.

Cmos device capable of reducing charge collection collected by radiation and preparation method thereof

Abstract: The invention discloses a CMOS device capable of reducing charge collection generated by radiation and preparation method thereof. The CMOS device provided by the invention is provided with a heavily doped charge restriction collecting region vertically below a source region and a drain region, the doping type of the charge restriction collecting region is opposite to those of the source region and the drain region, and the doping concentration is greater than or equal to those of the source region and the drain source. The transverse range of the charge restriction collecting region is slightly less than or equal to those of the source region and the drain region, and the transverse position of a channel is not more than the edges of the source region and the drain region. The CMOS device provided by the invention can greatly decrease the 'hopper' range generated under the action of single particle so that the instantaneously collected charge can be decreased under the action of the electric field. As the width of a depletion layer is narrowed, the electron-hole pairs in the 'hopper' range is more difficult to diffuse to the edge of the depletion layer, thus the charge collected by a sensitive node can be greatly reduced and the influence of the single particle transient state on the integrated circuit can be effectively restrained.

MOS-Transistor, welcher eine Struktur von kombinierter Quelle mit niedrigem Stromverbrauch aufweist und Verfahren zu seiner Herstellung

Abstract: MOS-Transistor, welcher eine Struktur von kombinierter Source mit niedrigem Stromverbrauch aufweist, wobei er eine Elektrodenschicht (3) fur ein Steuer-Gate, eine dielektrische Gate-Schicht (2), ein Halbleitersubstrat (1), einen hochdotierten Sourcebereich (5) und einen hochdotierten Drainbereich (6) aufweist, wobei eine Seite des hochdotierten Sourcebereichs (5), welche von einem Kanal weit entfernt ist, mit einem Schottky-Sourcebereich (7) verbunden ist, ein Ende des Steuer-Gates sich zu dem hochdotierten Sourcebereich (5) erstreckt, um eine T-Form zu bilden, ein sich erstreckender Bereich des Steuer-Gates ein sich erstreckendes Steuer-Gate (3b) ist und ein verbleibender Bereich des Steuer-Gates ein Haupt-Gate (3a) ist, ein aktiver Bereich, welcher durch das sich erstreckende Gate (3b) bedeckt ist, ein Kanalbereich ist, und ein Material des Kanalbereichs das gleiche ist wie dasjenige des Substrats (1), und ein Schottky-Ubergang zwischen dem Schottky-Sourcebereich (7) und dem Kanal unter dem sich erstreckenden Gate (3b) gebildet ist.

Composite-source structure low-power consumption mos transistor and preparation method thereof

Abstract: Disclosed is a composite-source structure low-power consumption MOS transistor. The present invention is related to the field of field-effect transistor logic devices and circuits in CMOS ultra-large scale integrated circuit (ULSI). The MOS transistor comprises a control grid electrode layer (3), a grid media layer (2), a semiconductor substrate (1), a Schottky source region (7), a highly-doped source region (5) and a highly-doped drain region (6), wherein one end of a control grid extends towards the highly-doped source region to form a T shape, the extended grid region is an extended grid (3b), an original control grid is a main grid (a), an active region covered under the extended grid (3b) is also a channel region, the material is the substrate material, and a Schottky junction is formed at a channel below the Schottky source region (7) and the extended grid (3b). The composite source structure combines a Schottky barrier and T-shaped grids, thereby improving the device performance and simplifying the preparation method, able to obtain higher conducting current, lower leakage current and a steeper sub-threshold slope. The MOS transistor can be adopted in the low power consumption field and has a higher practical value.