Showing papers by "R.D. Blanton published in 2002"

Built-in self test of CMOS-MEMS accelerometers

Abstract: A built-in self-test technique for MEMS that is applicable to symmetrical microstructures is described. A combination of existing layout features and additional circuitry is used to make measurements from symmetrically-located points. In addition to the normal sense output, self-test outputs are used to detect the presence of layout asymmetry that are caused by local, hard-to-detect defects. Simulation results for an accelerometer reveal that our self-test approach is able to distinguish misbehavior resulting from local defects and manufacturing process variations.

Fault tuples in diagnosis of deep-submicron circuits

Abstract: Diagnosis of malfunctioning deep-submicron (DSM) ICs is becoming more difficult due to the increasing sophistication of the manufacturing process and the structural complexity of the IC itself At the same time, key diagnostic tasks that include defect localization are still solved using primitive models of the IC's defects This paper explores the use of "fault tuples" in diagnosis Fault tuples can accurately mimic the complex misbehavior of DSM ICs at the logic level, enabling practical diagnosis of large circuits Initial assessment of the use of fault tuples in diagnosis is performed based on a case study involving one specific category of polysilicon spot defects Obtained results indicate that fault tuples may enhance diagnosis significantly

Modeling the economics of testing: a DFT perspective

Abstract: Decision-makers typically make test tradeoffs using models that mainly represent direct costs such as test generation time and tester use. Analyzing a test strategy's impact on other significant factors such as test quality and yield learning requires an understanding of the dynamic nature of the interdomain dependencies of test, manufacturing, and design. Our research centers on modeling the tradeoffs between these domains. To answer the DFT question, we developed the Carnegie Mellon University Test Cost Model, a DFT cost-benefit model, derived inputs to the model for various IC cases with different assumptions about volume, yield, chip size, test attributes, and so forth; and studied DFT's impact on these cases. We used the model to determine the domains for which DFT is beneficial and for which DFT should not be used. The model is a composite of simple cause-and-effect relationships derived from published research. It incorporates many factors affecting test cost, but we don't consider it a complete model. Our purpose is to illustrate the necessity of using such models in assessing the effectiveness of various test strategies.

Timed test generation for crosstalk switch failures in domino CMOS

Abstract: As technology scales into the deep submicron regime, capacitive coupling between signal lines becomes a dominant problem. Capacitive coupling is more acute for domino logic circuits since an irreversible, unwanted gate output transition can result. We present a timed test generation methodology for CMOS domino circuits that assigns the circuit inputs so that capacitively-coupled aggressors of a victim line transition in time proximity which creates a noise effect that is propagated within the clock-cycle constraint. Experiments for a multiplier reveal that a high level of accuracy is achieved without significant test generation time, resulting in a nearly 50% reduction in the number of sites earlier believed to be susceptible to crosstalk failure.

Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits

Abstract: As technology scales into the deep submicron regime, capacitive coupling between signal lines becomes a dominant problem. Capacitive coupling is more acute for domino logic circuits since an irreversible, unwanted gate output transition can result. We present a timed test generation methodology for CMOS domino circuits that assigns the circuit inputs so that capacitively-coupled aggressors of a victim line transition in time proximity which creates a noise effect that is propagated with in the clock-cycle constraint. Experiments for a multiplier reveal that a high level of accuracy is achieved w thout significant test generation time, resulting in a nearly 50% reduction in the number of sites earlier believed to be susceptible to crosstalk failure.

SoCs with MEMS? Can we include MEMS in the SoCs design and test flow?

Abstract: Position Statement S. Mir : MEMS are analog components. Embedding them in highly integrated devices means new test challenges for the analog and mixed-signal test community due to the multiple energy domains considered. Failure mechanisms and reliability are poorly understood and structured test approaches are generally missing. Functional testing of MEMS parts may be unavoidable, together with the use of expensive test equipment able to deal with signals other than electrical. Extremely high test costs together with poor reliability of MEMS blocks are major obstacles to see this type of cores in the SoCs of the near future. Position Statement H. Kerkhoff : Firstly, in contrast to conventional microelectronics and current SoC, many MEM device specifications are quite dependent on the final packaging implementation, as this determines the interaction between the actual domain and the electronic voltage or current and vice versa. Hence, models of MEMS in which the influence of packaging is not or partially included will therefore not be sufficiently accurate to be used in practice. This will involve much additional research, and data to be given by core providers. As a result, designers will probably be forced to use predetermined (and modeled) packages for these devices, which will be a new issue in SoC design and test. Secondly, in many cases, for several parts of MEMS (e.g. mechanical valves) it will not be feasible to develop a direct test in a mass-production environment, unless full functional tests are allowed. In this case, special Design-for-Test structures should be included in the MEMS to transform non-electrical properties into electrical ones, e.g. via capacitances (movement to electrical property). These should be part of the data given by core providers as well as standards for MEM tests. Position Statement S. Blanton : Are new testing methodologies and tools needed for SoCs with MEMS? The answer is unquestionably "yes". MEMS, in the most general sense, are sophisticated, miniature transducers that convert one type of energy (mechanical, thermal, optical, etc.) to another type (typically electrical) or vice-versa. Maximally testing MEMS in an all electrical domain would allow existing tester hardware to be utilized. Unfortunately, this is not possible given the mixed-physics properties of MEMS. For example, accelerometers must be literally "shaken" to provide the mechanical input stimulus needed to test and calibrate the interface between the mechanical and electrical components. Similarly, the test of other MEMS will requi re non-electrical stimulus generators and output response analyzers in order to test and assess their behavior. In addition, any attempts to implement MEMS structural test will require an understanding of the defect types and consequent misbehaviors. It is unlikely that this understanding will stem from an extrapolation of the defect types found in purely electronic systems. Moreover, the defect types will most likely depend on the type of MEMS and its underlying technology. For instance, defects for accelerometers and gyroscopes will be quite different from those affecting fluidic-based MEMS. Similar to analog and mixedsignal test, it is not at all clear if a structural approach to MEMS test can be successful. Therefore, new research is needed to understand the failure modes of MEMS in order to effectively develop testing methodologies for SoCs that contain MEMS. Position Statement H. Bederr : The number of transistors integrated in a single chip has constantly increased in the past years following more or less what has been predicted by Moore's law. Systems On Chips were among the first to take advantage of this by increasing both their size and complexity. However, the use of mixed signal or MEMS blocks in Systems On Chips has not followed this trend. The major reasons for that are the technical challenges of mixing and testing two different technologies. Although some DFT techniques like PLL or ADC BIST have started to emerge, almost nothing has been proposed for MEMS testing. Designers are already looking at having MEMS blocks in RF chips used in wireless applications, for instance microswitches, micro-electromechanical filters and antennas. What will be the impact of testing these parts on both the ATE and digital blocks ? Inserting test wrappers for both accessing and isolating these parts could follow some rules already defined for testing SoCs (like the ones resulting from the P1500 group activities) but what about the other issues : translating electrical characteristics into mechanical or optical ones, usable in a go/no-go BIST approach, automate the test insertion, adapting the ATE equipment to fit VLCT conditions …

Exploiting dominance and equivalence using fault tuples

Abstract: Local dominance and equivalence relationships for a single fault type have been exploited to reduce test set size and test generation time. However, these relationships have not been explored for multiple fault types. Using fault tuples, we describe how local dominance and equivalence relationships across various fault types can be derived. We also describe how the derived relationships can be used to order the faults efficiently for test generation in order to reduce test set size. Initial results using our ordered fault lists for ISCAS85 and ITC99 benchmark circuits reveals that test set size can be reduced by as much as 19%.

Test vector generation for charge sharing failures in dynamic logic

Abstract: Dynamic logic is increasingly becoming a logic type of choice for designs requiring high speed and low area. Charge sharing is one of many problems that may cause failure in dynamic logic circuits due to their low noise immunity. The authors address the charge-sharing noise issue. Specifically, they develop an accurate but tractable model for analyzing charge sharing that avoids costly Hspice simulations. The model is used to generate test vectors using a generalized ATPG tool. The charge-sharing model and the corresponding tests are validated using Hspice simulations on industrial circuits and it is also demonstrated that test vectors that establish high amounts of charge sharing could be generated for most domino gates.

Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation

Abstract: Neighboring line switching can contribute to a large portion of the delay of a line for today's deep submicron designs. The impact of this switching on delay is usually estimated by scaling the coupling capacitances (often by a factor of 2) and modeling them as grounded. This simple approach has been shown to be overly pessimistic in some cases, while somewhat optimistic in others. Apart from the delay modeling inaccuracies, the temporal and functional isolation of the aggressors can contribute to the pessimism. This paper introduces TACO, a timing analysis approach that addresses both these issues. TACO captures the provably worst-and best-case delays as a function of the timing-window inputs to the gates. We then present a comprehensive ATPG-based approach that uses functional information to identify valid interactions between coupled lines. Our algorithm accounts for glitches on aggressors that can be caused by static and dynamic hazards in the circuit. Results on industrial examples and benchmark circuits show the value of our approach.