A method of manufacturing a semiconductor device includes the steps of: providing a supply of molecules containing a plurality of dopant atoms into an ionization chamber, ionizing said molecules into dopant cluster ions, extracting and accelerating the dopant cluster ions with an electric field, selecting the desired cluster ions by mass analysis, modifying the final implant energy of the cluster ion through post-analysis ion optics, and implanting the dopant cluster ions into a semiconductor substrate In general, dopant molecules contain n dopant atoms, where n is an integer number greater than 10 This method enables increasing the dopant dose rate to n times the implantation current with an equivalent per dopant atom energy of 1/n times the cluster implantation energy, while reducing the charge per dopant atom by the factor n

Ion implantation device and a method of semiconductor manufacturing by the implantation of boron hydride cluster ions

Many of the processes used in the fabrication of silicon integrated circuits lead to the development of stress in the silicon substrate. Given enough stress, the substrate will yield by generating dislocations. We examine the formation of stress-induced dislocations in integrated circuit structures. Examples are presented from bipolar and MOS-based integrated circuit structures that were created during developmental studies. The underlying causes of oxidation-induced stress and the effect on such stress of varying oxidation conditions are discussed. The knowledge thus gained is used to explain dislocation generation during the formation of a shallow-trench isolation structure. The importance of ion-implantation processes in nucleating dislocations is illustrated using structures formed by a deep-trench isolation process and a process used to form a trench capacitor in a DRAM cell. The effect of device layout geometry on dislocation generation is also examined. We show how TEM observations can be used to provide more information than solely identifying those process conditions under which dislocations are generated. By combining TEM observations with stress analysis, we show how the sources of stress responsible for dislocation movement can be identified.

Stress induced dislocations in silicon integrated circuits

It is reported that fluorine can jeopardize p/sup +/-gate devices under moderate annealing temperatures. MOSFETs with BF/sub 2/ or boron-implanted polysilicon gates were processed identically except at gate implantation. Evidence of boron penetration through 12.5-nm oxide and a large quantity of negative charge penetration (10/sup 12/ cm/sup -2/) by fluorine even at moderate annealing conditions is reported. The degree of degradation is aggravated as fluorine dose increases. A detailed examination of the I-V characteristics of PMOSFET with fluorine incorporated p/sup +/-gate revealed that the long gate-length device had abnormal abrupt turn-on I/sub d/-V/sub g/ characteristics, while the submicrometer-gate-length devices appeared to be normal. The abnormal turn-on I/sub d/-V/sub g/ characteristics associated with long-gate-length p/sup +/-gate devices vanished when the device was subjected to X-ray irradiation and/or to a high-voltage DC stressing at the source/drain. The C-V characteristics of MOS structures of various gate dopants, processing ambients, doping concentrations, and annealing conditions were studied. Based on all experimental results, the degradation model of p/sup +/-gate devices is presented. The incorporation of fluorine in the p/sup +/ gate enhances boron penetration through the thin gate oxide into the silicon substrate and creates negative-charge interface states. The addition of H/OH species into F-rich gate oxide will further aggravate the extent of F-enhanced boron penetration by annealing out the negative-charge interface states. >

A comprehensive study on p/sup +/ polysilicon-gate MOSFET's instability with fluorine incorporation

Incorporation of metal silicides and refractory metals in VLSI technology

Submicrometer CMOS transistors require shallow junctions to minimize punchthrough and short-channel effects. Salicide technology is a very attractive metallization scheme to solve many CMOS scaling problems. However, to achieve a shallow junction with a salicide structure requires careful optimization for device design tradeoffs. Several proposed techniques to form shallow titanium silicide junctions are critically examined. Boron, BF/sub 2/, arsenic, and phosphorus dopants were used to study the process parameters for low-leakage TiSi/sub 2/ p/sup +//n and n/sup +//p junctions in submicrometer CMOS applications. It is concluded that the dopant drive-out (DDO) from the TiSi/sub 2/ layer to form a shallow junction scheme is not an efficient method for titanium salicide structure; poor device performance and unacceptably leaky junctions are obtained by this scheme. The conventional post junction salicide (PJS) scheme can produce shallow n/sup +//p and p/sup +//n junctions with junction depths of 0.12 to 0.20 mu m below the TiSi/sub 2/. Deep submicrometer CMOS devices with channel length of 0.40 to 0.45 mu m can be fabricated with such junctions. >

Process limitation and device design tradeoffs of self-aligned TiSi/sub 2/ junction formation in submicrometer CMOS devices

A 3.3-V CMOS technology with 0.6- mu m design rules in sixth-generation twin-tub CMOS (twin-tub VI) was developed. The major features of the device in this technology are: HIPOX twin-tub structure, n/sup +//p/sup +/ dual-type poly gate, 125-AA thin gate oxide, shallow junctions, rapid thermal anneal activation, and thin TiSi/sub 2/ as the source/drain/gate silicide layer. Electrical measurements show good I-V characteristics, ideal low junction leakage, latchup immunity for 4.5- mu m n/sup +/-to-p/sup +/ spacing, more than 6.0-V NMOSFET snapback breakdown voltage, good hot-carrier aging properties, and undetectable dopant interlateral diffusion through a TiSi/sub 2/ shunt layer of a different type of poly. The transistors were scaled to 0.45- and 0.40- mu m effective channel length without punchthrough at V/sub ds/=3.6 V for NMOS and PMOS, respectively. A 100-ps stage delay was obtained on a 101-stage CMOS ring oscillator at an operating voltage of 3.3 V. >

R. Liu

Papers

Process limitation and device design tradeoffs of self-aligned TiSi/sub 2/ junction formation in submicrometer CMOS devices

High-performance salicide shallow-junction CMOS devices for submicrometer VLSI application in twin-tub VI