An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer Observations indicate that reducing the inductance in the substrate bias is the most effective Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed >

Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits

A review on quality factor enhanced on-chip microwave planar resonators

Digital phase-locked loops (DPLLs) have been commonly used to estimate phase information. However, they exhibit poor performance or, occasionally, a divergence phenomenon, if noise information is incorrect or if there are quantization effects. To overcome the weaknesses of existing DPLLs, we propose a new DPLL with a finite-memory structure called the unbiased finite-memory DPLL (UFMDPLL). The UFMDPLL is independent of noise covariance information, and it shows intrinsic robustness properties against incorrect noise information and quantization effects due to the finite-memory structure. Through numerical simulations, we show that the proposed DPLL is more robust against incorrect noise information and quantization effects than the conventional DPLLs are.

Unbiased Finite-Memory Digital Phase-Locked Loop

This paper presents a 5.7–6.0 GHz Phase-Locked Loop (PLL) design using a 130 nm 2P6M CMOS process. We propose to suppress reference spur through reducing the current mismatch in charge pump (CP), controlling the delay time in phase frequency detector (PFD), and using a smaller VCO gain (KVCO). With a reference frequency of 32.768 MHz, chip measurement results show that the frequency tuning range is 5.7–6.0 GHz, the reference spur is −68 dBc, the phase noise levels are −109 dBc/Hz and −135 dBc/Hz at 1 MHz and 10 MHz offset respectively for 5.835 GHz. Compared with existing designs in the literature, this work’s reference spur is improved by at least 17% and its phase noise is the lowest. Under a 1.5 V supply voltage, the power dissipation with an output buffer of the PLL is 12 mW.

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A 5.7–6.0 GHz CMOS PLL with low phase noise and −68 dBc reference spur

A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs

A logic gate-based digital frequency multiplication technique for low-power frequency synthesis is presented. The proposed digital edge combining approach offers broadband operation with low-power and low-area advantages and is a promising candidate for low-power frequency synthesis in deep submicrometer CMOS technologies. Chip prototype of the proposed frequency multiplication-based 2.4-GHz binary frequency-shift-keying (BFSK)/amplitude shift keying (ASK) transmitter (TX) was fabricated in 0.13- $\mu{\rm m}$ CMOS technology. The TX achieves maximum data rates of 3 and 20 Mb/s for BFSK and ASK modulations, respectively, consuming a 14-mA current from 1.3 V supply voltage. The corresponding energy efficiencies of the TX are 3.6 nJ/bit for BFSK and 0.91 nJ/bit for ASK modulations.

A Digital Frequency Multiplication Technique for Energy Efficient Transmitters

Layout optimized planar spiral inductors using variable width (W) and spacing (S) across their turns are known to exhibit higher quality factors (Q) In this paper, we explore the performance improvement of 3-dimensional, series-stacked, parallel-stacked, single ended, and symmetric inductor configurations with variable W&S across their turns Parameterized cells for the aforementioned complex variable W&S inductor structures are developed in cadence using SKILL scripts for automatic generation of optimized inductor layouts with improved quality factors The analyzed standard (constant W&S) and layout optimized (variable W&S) inductors are fabricated in a 018 μm silicon on insulator process Measurement results show more than 20% improvement in quality factor for the 3-D stacked variable W&S inductor topologies Furthermore, an accurate, scalable, and broadband compact inductor model was developed and is shown to capture the improved Q characteristics across the analyzed inductor topologies A complementary LC-tank voltage controlled oscillator with layout optimized inductors, operating over 24-25 GHz frequency range was simulated using these developed compact models and is shown to exhibit an improved phase noise characteristics with better figure of merit

Design and modeling of high-Q variable width and spacing, planar and 3-D stacked spiral inductors

In this brief, the substrate noise effects of a pulsed clocking scheme on the output spur level, the phase noise, and the peak-to-peak (Pk-Pk) deterministic period jitter of an integer-N charge-pump phase-locked loop (PLL) are demonstrated experimentally. The phenomenon of noise coupling to the PLL is also explained through experiments. The PLL output frequency is 500 MHz and it is implemented in the 0.13- μm CMOS technology. Measurements show a reduction of 12.53 dB in the PLL output spur level at an offset of 5 MHz and a reduction of 107 ps in the Pk-Pk deterministic period jitter upon reducing the duty cycle of the signal injected into the substrate from 50% to 20%. The results of the analyses suggest that using a pulsed clocking scheme for digital systems in mixed-signal integration along with other isolation techniques helps reduce the substrate noise effects on sensitive analog/radio-frequency circuits.

Experimental Study on Substrate Noise Effects of a Pulsed Clocking Scheme on PLL Performance

The on-chip planar spiral inductors having variable width (W) and spacing (S) across their turns are known to exhibit higher quality factors (Q) In this paper, we present an efficient parameterized cell (pcell) design in cadence using SKILL scripts for automatic layout generation of these complex, high-Q, variable W&S spiral inductors comprising of single ended and symmetric structures with rectangular, hexagonal, octagonal and circular spirals Electromagnetic simulations are performed on the inductor layouts generated using the developed pcells The constant W&S and variable W&S spiral inductor structures are fabricated in a 018 μm silicon on insulator process Measurements show ∼25% improvement in the quality factor of variable W%S spiral inductors compared to their constant W&S counterparts and also validates the proper operation of the developed inductor parameterized cells The presented variable W&S inductor pcell significantly reduces the layout design time of RF circuit designers and also helps in the design automation of these complex inductor structures to boost their own performance and the RF circuits as well

R. R. Manikandan

Papers

A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs

A Digital Frequency Multiplication Technique for Energy Efficient Transmitters

Design and modeling of high-Q variable width and spacing, planar and 3-D stacked spiral inductors

Experimental Study on Substrate Noise Effects of a Pulsed Clocking Scheme on PLL Performance

A parameterized cell design for high-Q, variable width and spacing spiral inductors