The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

http://science.sciencemag.org/content/sci/311/5758/208.full.pdf

Stretchable form of single crystal silicon for high performance electronics on rubber substrates

Regression Analysis of Count Data: Preface

For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.

Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

This paper describes an analytical model for the access and cycle times of on-chip direct-mapped and set-associative caches. The inputs to the model are the cache size, block size, and associativity, as well as array organization and process parameters. The model gives estimates that are within 6% of Hspice results for the circuits we have chosen. This model extends previous models and fixes many of their major shortcomings. New features include models for the tag array, comparator, and multiplexor drivers, nonstep stage input slopes, rectangular stacking of memory subarrays, a transistor-level decoder model, column-multiplexed bitlines controlled by an additional array organizational parameter, load-dependent size transistors for wordline drivers, and output of cycle times as well as access times. Software implementing the model is available via ftp.

CACTI: an enhanced cache access and cycle time model

Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed. More specifically, the processes required to build circuits with multiple layers of active devices must be compatible with current state-of-the-art silicon processing technology. These processes must also show manufacturability, i.e., reliability, good yield, maturity, and reasonable cost. To meet these requirements, IBM has introduced a scheme for building 3D ICs based on the layer transfer of functional circuits, and many process and design innovations have been implemented. This paper reviews the process steps and design aspects that were developed at IBM to enable the formation of stacked device layers. Details regarding an optimized layer transfer process are presented, including the descriptions of 1) a glass substrate process to enable through-wafer alignment; 2) oxide fusion bonding and wafer bow compensation methods for improved alignment tolerance during bonding; 3) and a single-damascene patterning and metallization method for the creation of high-aspect-ratio (6:1 108 vias/cm2), and extremely aggressive wafer-to-wafer alignment (submicron) capability.

Three-dimensional integrated circuits

An integrated circuit can include an SRAM array having cells arranged in columns, each column being connected to true and complementary read local bitlines RLBLT and RLBLC. A local bit-select circuit can be connected to the cells of a column of the SRAM array, which can include first and second pull-down devices for pulling down a respective one of RLBLT and RLBLC at a timing controlled by a write control signal WRT. The circuit can include cross-coupled p-type field effect transistors (“PFETs”) including a first PFET having a gate connected to RLBLT and having a drain connected to RLBLC, and a second PFET of the pair having a gate connected to RLBLC and having a drain connected to RLBLT. A first device can control a strength of the cross-coupled PFETs. A pair of cross-coupled n-type field effect transistors (“NFETs”) can have gates connected to gates of the first and second pull-down devices. A second device can control a strength of the cross-coupled NFETs. The operation of the first and second devices can be controlled by applying first and second signals having programmed levels thereto. The levels of the first and second signals may selectively activate either the first device or the second device, so as to activate either the cross-coupled PFETs or the cross-coupled NFETs at one time.

Robust local bit select circuitry to overcome timing mismatch

PROBLEM TO BE SOLVED: To reduce the operating temperature of each element by burying a thermal conductor into a semiconductor chip structure, forming a plurality of elements in the structure adjacent to the thermal conductor, and transferring heat that is generated in the elements through the thermal conductor. SOLUTION: With a semiconductor chip structure 200, oxygen is implanted deeply into a substrate 210, a buried oxide layer 212 is formed, reactive ion etching is made to the lower portion, an opening for a shallow trench is formed, and a diamond thermal conductor 202 that is grown in contact with the substrate 210 in the shallow trench is glued to a recessed region near a source 230 and a drain 232. Then, a plurality of elements such as a transistor, a resistor are formed adjacent to the diamond thermal conductor 202, and heat that is generated in the elements is transferred through the diamond thermal conductor 202, thus reducing the operating temperature of each element.

Burial type thermal conductor for semiconductor chip

In this paper three unique facts are demonstrated for the first time: (1) it is possible to deposit by directional sputtering refractory barrier layers such as Ti, TiN and W over re-entrant VLSI topography with aspect ratios greater then 6; (2) variation of the film microstructure down the via occurs and can be verified by simulations; (3) simulation of the microstructure and profile of the deposited film can be used to determine the physics of the redeposition of material on the undercut regions. Using simulations it is determined that the most likely source of the re-emission is resputtering due to neutral bombardment.

Deposition and simulation of refractory barriers into high aspect ratio re-entrant features using directional sputtering

This work uses a gray, a semi-gray, and a non-gray model based on the Boltzmann Transport Equation (BTE) in the relaxation time approximation to compute the temperature distribution in a nano-scale multi-finger, PD/SOI nMOSFET with copper interconnects. The BTE models were successfully incorporated in CFD software, Fluent 6.1. The BTE is used in the device layer, whereas in other regions of the device, such as the silicon substrate, buried oxide, gate oxide, poly-gate, and metal interconnects, the Fourier heat conduction equation is employed. The BTE is coupled with the heat conduction equation at the interfaces using the diffuse mismatch model (DMM). Heat dissipation in the channel region of the FET and in the metal lines of the device is specified based on circuit simulations for a clock buffer used in a microprocessor. The computed results for the temperature distribution in the multi-finger NFET using the different approaches are compared with simulations that employ the classical heat conduction equation in the entire domain. The comparisons demonstrate that the broad temperature fields in the transistor are primarily determined by the overall thermal resistances due to the various device structures; channel temperature, however, is determined in large part by sub-continuum effects. The need for direct measurements of channel temperature rather indirect gate temperature measurements is pointed out as well.Copyright © 2004 by ASME

Simulation of Nano-Scale Multi-Fingered PD/SOI MOSFETs Using the Boltzmann Transport Equation

As technology scaled beyond the 100nm node, process variation and particularly random variations effects have had significant impact on the design yield. Memory designs, namely SRAMs, have become more prone to fails. Dynamic stability and dynamic noise margins have become a serious concern. Several design methodologies have been proposed to analyze and counter process variations. In this paper, we revisit key variability-driven design contributions, in terms of dual supply techniques, bitline clamping methods, and novel circuits with programmable capabilities, with particular emphasis on statistical exploration of the design space.

Rajiv V. Joshi

Papers

Robust local bit select circuitry to overcome timing mismatch

Burial type thermal conductor for semiconductor chip

Deposition and simulation of refractory barriers into high aspect ratio re-entrant features using directional sputtering

Simulation of Nano-Scale Multi-Fingered PD/SOI MOSFETs Using the Boltzmann Transport Equation

Statistical-aware designs for the nm era