Rajiv V. Joshi

TL;DR: In this article, the authors proposed a solution to provide an SRAM memory and a microprocessor, comprising a logic portion formed on a silicon substrate and an array portion, with a body region, where at least one pair of neighboring NFETs of the SRAM cell is linked in a leakage path diffusion region 338 under shallow source/drain region 334, the leakagepath diffusion region extends from the bottom of the source-drain diffusion to an embedded oxide layer 320; and at least two pairs of PFET of the neighboring SRAM cells has a body regions 336,

TL;DR: In this article, the degradation of PFET voltage to reduce it strength and improve write characteristics is discussed, where an edge detector is built into the circuit that real-time assesses the strength of the memory write operation.

TL;DR: A TCAD structure synthesis and capacitance extraction methodology in a 22nm CMOS process is presented and parasitic capacitances that affect the oscillation frequency of a 10 GHz voltage-controlled oscillator (VCO) are reported.

TL;DR: In this article, a method for predicting a condition in a circuit under design includes obtaining a set comprising first static noise margin curve for the circuit and a second static noisiness margin curve complementary to the first margin curve, matching the set to a two-dimensional model of a cell, and predicting the condition in accordance with hardware characterization data corresponding to the cell.

TL;DR: It is shown that the presence of gate-to-body tunneling current changes the strength of individual cell transistor in the quiescent (standby) state, thus affecting subsequent write/read operations.