R
Rajiv V. Joshi
Researcher at IBM
Publications - 336
Citations - 6463
Rajiv V. Joshi is an academic researcher from IBM. The author has contributed to research in topics: Static random-access memory & CMOS. The author has an hindex of 41, co-authored 309 publications receiving 6117 citations. Previous affiliations of Rajiv V. Joshi include National University of Singapore.
Papers
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Journal ArticleDOI
Hybrid RRAM/SRAM in-Memory Computing for Robust DNN Acceleration
Gokul Krishnan,Zhenyu Wang,Injune Yeo,Jian Meng,Maximilian Liehr,Rajiv V. Joshi,Nathaniel C. Cady,De-Cheng Fan,Jae-sun Seo,Yu Cao +9 more
TL;DR: A novel hybrid IMC architecture that integrates an RRAM-based IMC macro with a digital SRAM macro using a programmable shifter to compensate for the RRAM variations and recover the accuracy and a framework for the training of DNNs to support the hybrids through ensemble learning.
Proceedings ArticleDOI
"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 μm SOI and bulk technology (poster session)
TL;DR: In this article, power analysis at sub-zero temperatures for a high performance dynamic multiport register file (6 Read and 2 Write ports, 32 wordlines x 64 bitlines) fabricated in 0.25 μm Silicon on Insulator (SOI) and bulk technologies is presented.
Proceedings ArticleDOI
Yield and energy tradeoffs of an NVLatch design using radial sampling
TL;DR: This work studies the yield energy tradeoff of the backup mechanism of an STT-MTJ based nonvolatile latch and relies on Hicks and Wheeling methodology for multi-cone radial sampling for the purpose of rare fail estimation.
Patent
Massive multi-dimensionality failure analytics with smart converged bounds
Rajiv V. Joshi,Emrah Acar +1 more
TL;DR: In this article, a failure region exploration through uniform sampling of plurality of variables related to a circuit, the processor shifting probability distributions to explore failure probability, and a peripheral device providing a report on the failure of the circuit when the sampling is terminated by the processor.
Journal ArticleDOI
Power analysis of strained-Si devices/circuits
TL;DR: In this paper, the feasibility of nano-scale strained-Si technologies for low-power applications is studied, and the trade-offs for power and performance in strained Si devices/circuits are discussed.