Showing papers by "Ramon G. Carvajal published in 2014"

Highly linear wide-swing continuous tuning of CMOS transconductors

Abstract: A technique to improve the input and output range of CMOS transconductors with resistive current division for continuous tuning is presented. Using it, a tunable transconductor is proposed which features high linearity over a wide input range and simplicity. Measurement results of the transconductor, fabricated in a 0.5 µm CMOS process, show an IM3 of -66 dB for a ±1.65V supply and two input tones centered at 1 MHz of 1 Vpp each, and only 0.7 mW of power consumption. This represents an improvement of 13 dB versus the same transconductor using conventional current division. Copyright © 2013 John Wiley & Sons, Ltd.

CMOS op-amps for biomedical applications

Abstract: A new family of two stage op-amps with broadband open loop response is introduced. These have a significant reduction of the DC open loop gain and maintain a high gain at frequencies as low as 1 Hz. This provides them with low DC offset. The proposed circuits are based on the Quasi-Floating Gate (QFG) technique, using a novel implementation for active loads that provides a very low effective resistance at DC and very-low frequencies without penalizing the high resistance at the pass band gain significantly. Moreover, a wide-band AC coupling structure also based on QFG transistors has been combined with the proposed technique, rejecting both the differential input DC voltage and the offset introduced by the circuit. These features make the proposed op-amps suitable for biological signal processing, where small amplitude signals are commonly affected by large DC offsets. Cadence simulation results employing a 0.5 micrometers technology are provided for validating the proposed circuits.

Low Voltage Power Efficient Tunable Shaper Circuit With Rail-To-Rail Output Range for the HYDE Detector at FAIR

Abstract: This paper presents a low voltage, low power readout front-end system implemented in 130 nm CMOS technology. A conventional architecture that consists of charge sensitive amplifier, pole/zero cancellation and shaper has been used. The work focuses on the design of novel circuit topologies in low voltage environment minimizing the power consumption in modern deep submicron CMOS technologies. An operational amplifier with rail-to-rail output swing that uses a gain boosting technique and class-AB output stage without extra power consumption has been used for the shaper. The circuit combines excellent performances with simplicity of design and suitability for low voltage operation. The system is intended to work with silicon detectors for nuclear physics applications and is optimized to match an input capacitance of 10 pF. The system features a peaking time of 500 ns, a power dissipation of 1.57 mW/channel and an equivalent noise charge of 201 e-.

Low power analog front-end electronics in deep submicrometer CMOS technology based on gain enhancement techniques

Abstract: This paper evaluates the design of front-end electronics in modern technologies to be used in a new generation of heavy ion detectors—HYDE (FAIR, Germany)—proposing novel architectures to achieve high gain in a low voltage environment. As conventional topologies of operational amplifiers in modern CMOS processes show limitations in terms of gain, novel approaches must be raised. The work addresses the design using transistors with channel length of no more than double the feature size and a supply voltage as low as 1.2 V. A front-end system has been fabricated in a 90 nm process including gain boosting techniques based on regulated cascode circuits. The analog channel has been optimized to match a detector capacitance of 5 pF and exhibits a good performance in terms of gain, speed, linearity and power consumption.