Efforts towards energy-harvesting solutions are targeted for wireless sensor node applications and focus on performing maximum power extraction and storing power, yet efforts to deliver a regulated supply to voltage-sensitive blocks in power-limited applications has yet to be fully achieved. This paper presents a low-power, autonomous power management unit (PMU) able to perform maximum power point tracking for dc-type renewable sources. It includes a startup circuit fed directly from the renewable source. The PMU delivers a regulated output voltage through a digital LDO. The main step-up operation is performed through a dynamically controlled, power-aware, capacitive dc–dc converter that performs the required voltage gain procedure. Then, the digital LDO receives the EH source power density information from the dc–dc converter and provides regulation. Information about the source-power density availability is passed on to the digital LDO in order to select the best pass device size from a bank of three arrays. The PMU allows power consumption decrease by reducing the gate driving losses associated with large pass transistor devices, and it enhances efficiency. The system was fabricated in 180 nm CMOS process, and maximum end-to-end efficiency was measured at 57% with 1.75 mW of input power.

An Autonomous Energy Harvesting Power Management Unit With Digital Regulation for IoT Applications

An output-capacitorless low-dropout regulator (OCL-LDO) using enhanced multipath nested Miller compensation with embedded feedforward path for system-on-chip (SoC) applications is presented in this paper While state-of-the-art LDOs are restricted to low-frequency operation with a maximum unity-gain bandwidth (UGB) typically ranging from several hundred kilohertz to no higher than 10 MHz even in advanced technologies (65 nm or beyond), the prototype fabricated in a standard 130-nm CMOS process features over 100-MHz UGB for all loading conditions up to 25-mA output current while consuming a quiescent current of 112 μ A With this ultra-wide bandwidth, the proposed LDO achieves 200-ps response time for load transient with 300-ps edge time The extension of UGB also magnificently contributes to improvement of power-supply rejection (PSR), making it comparable to OCL-LDOs that use ripple-feedforward techniques to specifically boost PSR or LDOs with large off-chip decoupling capacitors, while enjoying much faster speed The chip area is 0008 mm2

A 200-ps-Response-Time Output-Capacitorless Low-Dropout Regulator With Unity-Gain Bandwidth >100 MHz in 130-nm CMOS

This paper presents an on-chip, low drop-out (LDO) voltage regulator with improved power-supply rejection (PSR) able to drive large capacitive loads. The LDO compensation is achieved via a custom, wide bandwidth capacitance multiplier (c-multiplier) that emulates a nanofarad-range capacitance at the LDO output node. The LDO frequency response resembles that of externally compensated LDOs, leading to a wide PSR frequency range without using an off-chip capacitor. To drive large capacitive loads without stability concerns, the supply-line capacitance of the load circuit is incorporated to the design of the LDO compensation scheme. The power-stability-performance tradeoffs involved in the design are discussed in detail. The LDO and the c-multiplier are implemented in 0.18- $\mu \text{m}$ CMOS technology and target applications with load currents in the 10-mA range. Experimental results show that the LDO achieves a PSR better than −39 dB up to 20 MHz at 1.2 V output voltage, while maintaining a 97.4% current efficiency.

A Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip Capacitive Loads

This paper presents an internally compensated capacitor-less low dropout regulator (CL-LDO) with bulk-driven feed-forward supply noise cancellation and adaptive compensation for fast settling time ( TS ). A feed-forward path from the CL-LDO's supply input to the output is implemented to increase power supply rejection (PSR) from mid-range frequencies to up to 5 MHz. The CL-LDO achieves a −90 dB low frequency and –64 dB PSR at 1 MHz for 50 mA of load current ( IL ). A transconductance amplifier with adaptive Miller compensation based on IL sense is used to increase the unity-gain frequency by 40× at heavy loads. The CL-LDO achieves a 0.3 mV/V line regulation, 10 μ V/mA load regulation, 300 ns of TS , and 0.16 ps figure of merit, which is 7.5× better than current state-of-the-art CL-LDOs. The CL-LDO was fabricated in CMOS 130 nm technology, consumes IQ of 42 μ A, has a dropout voltage ( V DO) of 200 mV for IL of 50 mA, and occupies an active area of 0.0046 mm2.

A High Power Supply Rejection and Fast Settling Time Capacitor-Less LDO

This brief presents a low-power fast-transient capacitor-less low-dropout regulator (CL-LDO) for system-on-a-chip applications. A low-quiescent-current class-AB amplifier with embedded slew-rate enhancement (SRE) circuit is proposed to improve both current efficiency and load transient performance. As the SRE circuit is directly controlled by the amplifier, only a minimum hardware overhead is required. The proposed CL-LDO is fabricated in a 0.18- ${\mu }\text{m}$ standard CMOS process. It occupies an active area of 0.031 mm2 and consumes a quiescent current of $10.2~\mu \text{A}$ . It is capable of delivering a maximum load current of 100 mA at 1.0-V output from a 1.2-V power supply. The measured results show that a settling time of $0.22~\mu \text{s}$ is achieved for load steps from 1 mA to 100 mA (and vice versa) with an edge time of $0.1~\mu \text{s}$ .

Low-Power Fast-Transient Capacitor-Less LDO Regulator With High Slew-Rate Class-AB Amplifier

Demand for system-on-chip solutions has increased the interest in low drop-out (LDO) voltage regulators which do not require a bulky off-chip capacitor to achieve stability, also called capacitor-less LDO (CL-LDO) regulators. Several architectures have been proposed; however comparing these reported architectures proves difficult, as each has a distinct process technology and specifications. This paper compares CL-LDOs in a unified matter. We designed, fabricated, and tested five illustrative CL-LDO regulator topologies under common design conditions using 0.6?m CMOS technology. We compare the architectures in terms of (1) line/load regulation, (2) power supply rejection, (3) line/load transient, (4) total on-chip compensation capacitance, (5) noise, and (6) quiescent power consumption. Insights on what optimal topology to choose to meet particular LDO specifications are provided.

Low Drop-Out Voltage Regulators: Capacitor-less Architecture Comparison

A technique is proposed for improving the common mode rejection ratio (CMRR) of op-amp based instrumentation amplifiers in resistor---capacitor (RC) feedback configurations. This is done by dynamically matching the input and the feedback capacitor pairs. A fully differential biopotential amplifier was designed with the proposed dynamic capacitor matching (DCM) scheme and its performance compared against the conventional case. The experimental results show that the proposed dynamic capacitor matching technique improves CMRR by more than 40 dB over the conventional case. The proposed technique also reduces the power consumption of the biopotential amplifier. The amplifier consumes less power during the `OFF' periods when using DCM and this results in the overall lower power consumption of the amplifier. The quiescent current consumption of the biopotential amplifier is 20 μA with a 1.5 V dual power supply source and a maximum input referred noise of 3 μV.

A biopotential amplifier with dynamic capacitor matching for improved CMRR

In this paper, a technique is proposed for improving the Common Mode Rejection Ratio (CMRR) of opamp based Instrumentation Amplifiers in resistor-capacitor (RC) feedback configurations by dynamically matching input and feedback capacitor pairs. A fully differential biopotential amplifier is designed with the proposed dynamic element-matching scheme and its performance is compared with the case where dynamic element matching is switched off. Experimental results show that the proposed dynamic element matching technique improves CMRR by over 40 dB over the conventional case. The proposed technique also reduces average power consumption. The biopotential amplifier draws an average of 20uA of quiescent current from a 1.5V dual power supply source. The input referred noise is less than 3uV/sqrt (Hz).

Reza Abdullah

Papers

Low Drop-Out Voltage Regulators: Capacitor-less Architecture Comparison

A biopotential amplifier with dynamic capacitor matching for improved CMRR

A biopotential amplifier with improved common mode gain