An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Power semiconductor devices and methods of manufacture

A system and method for combining power from DC power sources. Each power source is coupled to a converter. Each converter converts input power to output power by monitoring and maintaining the input power at a maximum power point. Substantially all input power is converted to the output power, and the controlling is performed by allowing output voltage of the converter to vary. The converters are coupled in series. An inverter is connected in parallel with the series connection of the converters and inverts a DC input to the inverter from the converters into an AC output. The inverter maintains the voltage at the inverter input at a desirable voltage by varying the amount of the series current drawn from the converters. The series current and the output power of the converters, determine the output voltage at each converter.

Distributed Power Harvesting Systems Using DC Power Sources

A monitoring system and method for monitoring performance of individual powers sources in a distributed power source system A monitoring module is coupled to each of the power sources, or to each string of serially connected power sources, to monitor and collect data regarding current, voltage, temperature and other environmental factors at the power source The collected data is transmitted over a power line to a central analysis station for analysis Data collected from each source indicates malfunction or degradation at the source Comparison of data collected from adjacent sources filters for environmental factors impacting neighboring sources such as cloudy days for a solar panel Comparison of data collected from the same source at different times indicates soiling or degradation of the source with time or periodic events such as a moving shade from an adjacent building

Monitoring of Distributed Power Harvesting Systems Using DC Power Sources

A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

High-voltage transistor with multi-layer conduction region

A process sequence that produces a plurality of pretransistor structures from which a variety of high voltage, isolated integrated circuits and low voltage integrated circuits are easily fabricated.

Complementary, isolated DMOS IC technology

The historical and technological development of the ubiquitous trench power MOSFET (or vertical trench VDMOS) is described. Overcoming the deficiencies of VMOS and planar VDMOS, trench VDMOS innovations include pioneering efforts in reactive ion etching and oxidation of the silicon trench gate, polysilicon fill and recessed etchback, unit cell and distributed voltage clamping to protect the trench gate, and scaling active cells to high densities using deep submicron fabrication. Thereafter, gate–drain engineered trench VDMOS improved high-frequency switching capability with lower gate charge utilizing nonuniform gate oxides, field shaping, and charge balancing (superjunction, RSO) methods. The recent adaptation of trench gates in wide bandgap unipolar devices is also described.

The Trench Power MOSFET: Part I—History, Technology, and Prospects

A power MOSFET or other semiconductor device contains a layer of silicon combined with germanium to reduce the on-resistance of the device. The proportion of germanium in the layer is typically in the range of 1-40%. To achieve desired characteristics the concentration of germanium in the Si-Ge layer can be uniform, stepped or graded. In many embodiments it is desirable to keep the germanium below the surface of the semiconductor material to prevent germanium atoms from being incorporated into a gate oxide layer. This technique can be used in vertical DMOS and trench-gated MOSFETs, quasi-vertical MOSFETs and lateral MOSFETs, as well as insulated gate bipolar transistors, thyristors, Schottky diodes and conventional bipolar transistors.

Low resistance power MOSFET or other device containing silicon-germanium layer

The cell density of a trenched DMOS transistor is increased by overcoming the problem of lateral diffusion of deep P+ body regions. This problem is solved by forming the deep P+ body region (16) using a high energy implant into a single epitaxial layer (12). The cell density is improved to more than 12 million cells per square inch.

High density trenched DMOS transistor

A high voltage integrated circuit (IC) has a passivation structure that shields the underlying circuit from the electrical effects of charge on the passivation structure. In one embodiment, the passivation structure comprises a silicon rich nitride layer in electrical contact with underlying circuit elements. The silicon rich nitride is highly resistive and permits only a negligible current between elements, but is conductive enough that charge on the surface of the passivation structure flows into the IC before the electric fields in the underlying circuit elements is significantly changed. In another embodiment, the passivation structure has two or more layers with a less conductive layer in contact with the underlying IC and overlying conductive layer which shields the IC from the effects of charge build up.

Richard K. Williams

Papers

Complementary, isolated DMOS IC technology

The Trench Power MOSFET: Part I—History, Technology, and Prospects

Low resistance power MOSFET or other device containing silicon-germanium layer

High density trenched DMOS transistor

Lightly-doped drain MOSFET with improved breakdown characteristics