Showing papers by "Robert W. Brodersen published in 1995"

Low Power Digital CMOS Design

Abstract: 1. Introduction. 2. Hierarchy of Limits of Power J.D. Meindl. 3. Sources of Power Consumption. 4. Voltage Scaling Approaches. 5. DC Power Supply Design in Portable Systems coauthored with A.J. Stratakos, et al. 6. Adiabatic Switching L. Svensson. 7. Minimizing Switched Capacitance. 8. Computer Aided Design Tools. 9. A Portable Multimedia Terminal. 10. Low Power Programmable Computation coauthored with M.B. Srivastava. 11. Conclusions. Subject Index.

Minimizing power consumption in digital CMOS circuits

Abstract: An approach is presented for minimizing power consumption for digital systems implemented in CMOS which involves optimization at all levels of the design. This optimization includes the technology used to implement the digital circuits, the circuit style and topology, the architecture for implementing the circuits and at the highest level the algorithms that are being implemented. The most important technology consideration is the threshold voltage and its control which allows the reduction of supply voltage without significant impact on logic speed. Even further supply reductions can be made by the use of an architecture-based voltage scaling strategy, which uses parallelism and pipelining, to tradeoff silicon area and power reduction. Since energy is only consumed when capacitance is being switched power can be reduced by minimizing this capacitance through operation reduction choice of number representation, exploitation of signal correlations, resynchronization to minimize glitching, logic design, circuit design, and physical design. The low-power techniques that are presented have been applied to the design of a chipset for a portable multimedia terminal that supports pen input, speech I/O and full-motion video. The entire chipset that performs protocol conversion, synchronization, error correction, packetization, buffering, video decompression and D/A conversion operates from a 1.1 V supply and consumes less than 5 mW. >

Optimizing power using transformations

Abstract: The increasing demand for portable computing has elevated power consumption to be one of the most critical design parameters. A high-level synthesis system, HYPER-LP, is presented for minimizing power consumption in application specific datapath intensive CMOS circuits using a variety of architectural and computational transformations. The synthesis environment consists of high-level estimation of power consumption, a library of transformation primitives, and heuristic/probabilistic optimization search mechanisms for fast and efficient scanning of the design space. Examples with varying degree of computational complexity and structures are optimized and synthesized using the HYPER-LP system. The results indicate that more than an order of magnitude reduction in power can be achieved over current-day design methodologies while maintaining the system throughput; in some cases this can be accomplished while preserving or reducing the implementation area. >

Energy efficient CMOS microprocessor design

Abstract: Reduction of power dissipation in microprocessor design is becoming a key design constraint. This is motivated not only by portable electronics, in which battery weight and size is critical, but by heat dissipation issues in larger desktop and parallel machines as well. By identifying the major modes of computation of these processors and by proposing figures of merit for each of these modes, a power analysis methodology is developed. It allows the energy efficiency of various architectures to be quantified, and provides techniques for either individually optimizing or trading off throughput and energy consumption. The methodology is then used to qualify three important design principles for energy-efficient microprocessor design. >

SIERA: a unified framework for rapid-prototyping of system-level hardware and software

Abstract: Modern electronic systems contain a mix of software running on general-purpose programmable processors, algorithms hardwired into dedicated hardware such as custom boards and chips, electromechanical components, and mechanical interconnect and packaging. Far more time Is spent in designing the boards, writing the software to drive, and integrate the hardware, and other such system level issues, than is spent in designing any application-specific ICs that may be needed. Therefore a systems perspective of the design process is essential, as opposed to the conventional "chip-focused" approach. A design framework, called SIERA, for application-specific systems is described in which higher level aspects of system design, including software, multichip design issues present at the board level, and hardware-software integration are addressed, in addition to the design of individual custom chips. A high-level description of the system as a network of processes is mapped to a system architecture template consisting of multiple boards using dedicated hardware modules and ASIC's as well as software processes running on programmable hardware modules. Application of SIERA's design methodology to a multisensory robot control system is also presented. >

A prototype user interface for a mobile multimedia terminal

Abstract: We have shown a prototype user interface for the InfoPad, a portable terminal with multi-modal input and multimedia output. We believe that many of the people who could benefit from inexpensive, portable, networked terminals are not computer experts, and we are therefore designing the InfoPad and its user interface to be more like a notebook than a workstation. The InfoPad’s main features are: ● Portabilityy ●Continuous network connectivity using a highbandwidth radio link ● Pen input with handwriting recognition ● Audio input with speech recognition ● Full-motion video playback with synchronized audio The InfoPad’s unique input and output characteristics offer challenges and opportunities for user interface design. We are prototyping applications and user interfaces to explore how handwriting and voice recognition may best be used together. We believe that the lessons we will learn can be applied to other multi-modal platforms.

System level hardware module generation

Abstract: In complex modern day electronic systems, far more time is spent in designing the boards, writing the software to drive and integrate the hardware, and other such system level issues, than is spent in designing any application-specific ICs that may be needed. Unfortunately, most of the research in computer-aided design has been focussed on the more glamorous ASIC design problem, as a result of which the design methodologies and tools at the system level are much more primitive than at the chip level. We have developed a design framework for application-specific systems, called SIERA, that addresses the higher level aspects of system design, including multichip design issues at the board-level, and hardware-software codesign and integration, in addition to the design of individual ASICs. SIERA allows rapid-prototyping of multiboard systems where the functionality is implemented using a mix of dedicated hardware modules and ASICs, as well as software running on programmable hardware modules. A key step in the design methodology provided by SIERA is that of generating the physical implementation of the system hardware from a description of the system architecture. The analogue of this problem at the chip level is referred to as silicon assembly or silicon compilation. In this paper we address this problem at the system level, and describe how the generation and interfacing of board-level modules, board-level physical design, simulation of custom boards, and the overall management of board design are handled in SIERA. While some of the problems could be solved by adapting or extending techniques from the existing ASIC design tools, others required new approaches. Case-studies of several real-life applications are also presented to demonstrate the effectiveness of the board-level physical design methodology embodied in SIERA compared to the traditional PCB design systems. >

Sources of Power Consumption

Abstract: The design of portable devices certainly requires consideration of the peak power consumption for reliability and proper circuit operation, but more critical is the time averaged power consumption which is directly proportional to the battery weight and volume required to operate circuits for a given amount of time. In fact, the approaches which will be presented to minimize the average power consumption will also reduce the peak power consumption and improve reliability.

Design of wireless portable systems

Abstract: The InfoPad project explores the infrastructure and devices required for portable wireless access to the national information infrastructure. The InfoPad model emphasizes high-bandwidth wireless connectivity and moves the computing power of the portable device into the backbone network, where we can provide not only full internet access, but increased computing power as well. By concentrating on I/O for the pad we reduce its cost, weight and power requirements, and increase the effective bandwidth through the greater error tolerance of I/O traffic such as video. We describe the InfoPad model, its infrastructure, and the results of the first prototype. This prototype proved the feasibility of the basic model and developed key technologies such as low-power design methodology and protocols for wireless connections. We also discuss the next generation InfoPad and our future plans.

A design system for on-chip oversampling A/D interfaces

Abstract: An integrated design system for the analysis, design, and implementation of on-chip A/D interfaces using oversampling A/D converters has been developed. The system unifies a diverse base of design knowledge required for mixed analog and digital circuits and covers the design process from specification to mask layout for a variety of configurations. A hierarchical design estimation approach was used to guide system development, allowing designers to quickly estimate performance at a high level of abstraction and to update these estimates as the design progresses. At lower levels of abstraction, architecture templates are used to encapsulate information about particular filter implementations and to simplify the design process. Designers use performance estimates to guide the design process and to make the critical decisions about the choice of algorithm and architecture. Accurate simulation models have been integrated into the design system to allow examination and verification. Results from a 14-b signal acquisition module are presented to illustrate use of the tools and the typical tradeoffs faced at different levels of abstraction. This system illustrates how various design automation techniques can be combined to provide better optimization for a complex system design and to shorten design cycles for custom converters to a matter of days. >

The InfoPad user interface

Abstract: We have shown a prototype user interface for the InfoPad, a portable terminal with multi-modal input and multimedia output. The InfoPad's main features are: portability, continuous network connectivity using a high-bandwidth radio link, pen input with handwriting recognition, audio input with speech recognition, full-motion video playback with synchronized audio, text/graphics display. The InfoPad's unique input and output characteristics offer challenges and opportunities for user interface design. We have implemented an API for network access to audio, pen, graphics, and video data; we have also implemented speech and handwriting recognizers along with programming interfaces and toolkits. We are prototyping applications and user interfaces to explore how handwriting and voice recognition may best be used together. We believe that the lessons we will learn can be applied to other multi-modal platforms.

Voltage Scaling Approaches

Abstract: Since the dominant component of power consumption for a properly designed CMOS circuit is proportional to the square of the supply voltage, operating circuits at the lowest voltage is the key to minimizing the energy consumed per operation. However, the individual circuit elements run slower at lower supply voltages (Figure 3.25) and this must be compensated for through appropriate architectural design. One important class of applications are those which have no advantage in exceeding a bounded computation rate, as found in real-time signal processing. The strategies presented in this chapter also have some applicability to the maximum throughput situation of general purpose computing though additional system level trade-offs must be made.

Minimizing Switched Capacitance

Abstract: In the previous chapter, power dissipation was minimized in CMOS circuits by aggressive supply voltage scaling. Since CMOS circuits do not dissipate power if they are not switching, another approach to low power design is to reduce the switching activity to the minimal level required to perform the computation. This can range from simply powering down the complete circuit or portions of it, to more sophisticated schemes in which the clocks are gated or optimized circuit architectures are used which minimize the number of transitions. The focus of this chapter is on minimizing the switched capacitance at all levels of the design. The following sections describe a system level approach to minimize the switched capacitance which involves optimizing algorithms, architectures, logic design, circuit design, and physical design.