Proceedings ArticleDOI
Energy efficient CMOS microprocessor design
T.D. Burd,Robert W. Brodersen +1 more
- Vol. 1, pp 288-297
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TLDR
A power analysis methodology is developed that allows the energy efficiency of various architectures to be quantified, and provides techniques for either individually optimizing or trading off throughput and energy consumption.Abstract:
Reduction of power dissipation in microprocessor design is becoming a key design constraint. This is motivated not only by portable electronics, in which battery weight and size is critical, but by heat dissipation issues in larger desktop and parallel machines as well. By identifying the major modes of computation of these processors and by proposing figures of merit for each of these modes, a power analysis methodology is developed. It allows the energy efficiency of various architectures to be quantified, and provides techniques for either individually optimizing or trading off throughput and energy consumption. The methodology is then used to qualify three important design principles for energy-efficient microprocessor design. >read more
Citations
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Real-time dynamic voltage scaling for low-power embedded operating systems
Padmanabhan Pillai,Kang G. Shin +1 more
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The simulation and evaluation of dynamic voltage scaling algorithms
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Comparing algorithm for dynamic speed-setting of a low-power CPU
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Scheduling with dynamic voltage/speed adjustment using slack reclamation in multiprocessor real-time systems
TL;DR: This paper proposes two novel power-aware scheduling algorithms for task sets with and without precedence constraints executing on multiprocessor systems and proposes a new scheme of slack reservation to incorporate voltage/speed adjustment overhead in the scheduling algorithms.
Proceedings ArticleDOI
Power Aware Scheduling of Bag-of-Tasks Applications with Deadline Constraints on DVS-enabled Clusters
TL;DR: This paper provides power-aware scheduling algorithms for bag-of-tasks applications with deadline constraints on DVS-enabled cluster systems in order to minimize power consumption as well as to meet the deadlines specified by application users.
References
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Journal ArticleDOI
Low-power CMOS digital design
TL;DR: In this paper, techniques for low power operation are presented which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations to reduce power consumption in CMOS digital circuits while maintaining computational throughput.
Journal Article
Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.
Book
Device electronics for integrated circuits
TL;DR: In this article, the authors present a list of symbols for metal-oxide-silicon systems, including Mos Field-effect transistors, high-field effects, and high-frequency effects.