A power conversion device includes a power switching circuit that supplies AC voltages generated between switching elements operating as upper arms and switching elements operating as lower arms, and a control circuit that generates and supplies to the driver circuit signals for controlling the switching operation of the switching elements by a PWM method in a first operational region in which frequency of an AC power to be outputted is low, and that generates and supplies to the driver circuit signals for controlling the switching operation of the switching elements at timings based upon the phase of the AC power to be outputted in an operational region in which the frequency of the AC power to be outputted is higher than in the first operational region.

Power Conversion Device

In one embodiment, a multiphase converter is disclosed. The multiphase converter may comprise a plurality of phase circuits and a plurality of phase control circuits. Each phase circuit may comprise a switch having a control terminal, and the control terminal of the switch may be configured to receive a drive signal. Each phase control circuit may be corresponding to one of the phase circuits, and each phase control circuit may be configured to provide a phase control signal to adjust an ON-time period or a reference signal for the corresponding phase circuit. The phase control signal may be responsive to the drive signal of the corresponding phase circuit.

Multiphase converter with controllable phase shift

A 3.6 µV rms Noise, 3 ppm/°C TC Bandgap Reference With Offset/Noise Suppression and Five-Piece Linear Compensation.

A DC/DC converter configurable for operating as a multiphase DC/DC. A controller produces a master drive signal for controlling a primary power switch to produce the output DC signal at a desired level. Multiple secondary power stages are coupled between the input and the output nodes for producing an output DC signal. Each of the multiple secondary power stages has at least one secondary power switch responsive to the input DC signal for producing the output DC signal. An expander system configures the DC/DC converter for operation in a multiphase DC/DC conversion mode. The expander system is responsive to the master drive signal for producing multiple slave drive signals respectively supplied to the multiple secondary power stages for controlling secondary power switches. The slave drive signals have phases shifted with respect to the master drive signal and with respect to each other.

Expanding DC/DC converter into multiphase DC/DC converter

Methods, systems, circuits, devices, and apparatuses are described for multi-phase hysteretic buck switching regulators. Systems, circuits, devices, and apparatuses for multi-phase hysteretic buck switching regulators may include master phase components, multi-phase delay generators, and one or more slave phase components. Methods for multi-phase hysteretic buck switching regulation are also provided.

Multi-phase hysteretic buck switching regulator

This article introduces an accurate current-mode bandgap reference circuit design with a novel shared offset compensation scheme for its internal amplifiers. This bandgap circuit has been designed to operate over a very wide temperature range from −40 °C to 150 °C. Its output voltage is 1.16 V with a 3.3-V supply voltage. A multi-section curvature compensation method alleviates the error from the bipolar junction transistor’s base–emitter nonlinear voltage dependence on temperature. The bandgap reference circuit contains two operational amplifiers that are utilized to generate proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) current sources. With the implementation of the described shared offset-cancellation methodology, the simulated output inaccuracy introduced by the amplifier is kept to a 5 $\sigma $ offset within ±4.6 $\mu \text{V}$ while allowing to conserve die size and power consumption by preventing that each amplifier is accompanied by its own active auxiliary offset-cancellation circuit. Designed and fabricated in a 130-nm CMOS process technology, the bandgap reference has a measured output voltage shift of less than 1 mV over a −40 °C to 150 °C temperature range and an overall variation of ±8.2 mV across seven measured samples without trimming.

A 1.16-V 5.8-to-13.5-ppm/°C Curvature-Compensated CMOS Bandgap Reference Circuit With a Shared Offset-Cancellation Method for Internal Amplifiers

A power supply circuit can be configured to include a first circuit and a second circuit. Each circuit can be substantially identical to each other but provide different functionality depending on how they are configured. For example, each of the first circuit and second circuit can be chips having substantially the same pin layout and internal circuitry. However, the functionality provided by the circuits varies depending on whether a respective circuit is configured as a master or slave. The first circuit is configured as the master and generates multiple phase control signals. The first circuit uses a portion of the multiple phase control signals to control a first set of phases. The first circuit transmits a second portion of the multiple phase control signals to the second circuit configured as a slave. The second circuit is configured to receive and use the second portion of control signals to control a second set of phases.

Master/slave power supply switch driver circuitry

This paper introduces an accurate frequency regulation method based on a constant on-time (COT) buck regulator designed for point-of-load (POL) regulation with a fast load transient requirement and wide load range. Traditional COT regulators suffer from frequency shift due to load variations. The proposed frequency adjustment circuit helps the COT control engine to reach its target frequency of operation by adjusting the on-time pulse under varying conditions. This circuit includes a phase detector and a voltage-to-current converter block. The phase error between the target clock signal and the PWM is directly used to adjust the width of the on-time pulse. This will fine-tune the bandwidth of the frequency regulation loop, which can help to improve the transient performance of the COT as well. The fabricated chip has been tested under 20A/ $\mu \text{s}$ load transient speed with a 10A load step condition. The measured silicon performance shows that the error of the switching frequency is less than 0.16% in the 400kHz to 1MHz range during steady-state operation.

Buck Circuit Design With Pseudo-Constant Frequency and Constant On-Time for High Current Point-of-Load Regulation

An integrated circuit resides on a circuit board. During operation, the digital controller integrated circuit produces control signals to control a power supply for delivery of power to a load. The integrated circuit can include multiple connectivity ports, on-board memory, and mode control logic. The multiple connectivity ports such as pins, pads, etc., of the integrated circuit can be configured to provide connections between internal circuitry residing in the integrated circuit and external circuitry residing on a circuit board to which the integrated circuit is attached. The mode control logic monitors a status of one or more connectivity ports of the integrated circuit to detect when a board handler places the digital controller in a power island mode in which the integrated circuit is powered so that the board handler can access (e.g., read/write) the memory in the digital controller integrated circuit while other portions of the board are unpowered.

Electrical circuitry for use in voltage controllers

An isolated switched-mode power converter converts power from an input source into power for an output load. A digital controller senses a secondary-side voltage, such as a rectified voltage, of the power converter. The secondary-side voltage is divided down using a high-impedance voltage divider. The resultant divided-down voltage is provided to a voltage sensor within the digital controller. The voltage sensor level shifts the provided voltage, and buffers the resulting level-shifted voltage. The buffered, level-shifted voltage is provided to a tracking analog-to-digital converter (ADC) for digitization. The buffered signal provided to the tracking ADC has a high current capability, such that the voltage input to the tracking ADC may quickly converge before the tracking ADC outputs a digital value for the sensed secondary-side voltage.

Ronald Hulfachor

Papers

A 1.16-V 5.8-to-13.5-ppm/°C Curvature-Compensated CMOS Bandgap Reference Circuit With a Shared Offset-Cancellation Method for Internal Amplifiers

Master/slave power supply switch driver circuitry

Buck Circuit Design With Pseudo-Constant Frequency and Constant On-Time for High Current Point-of-Load Regulation

Electrical circuitry for use in voltage controllers

Circuits and methods for secondary-side rectified voltage sensing in isolated switched-mode power converters