R
Ryoichi Hori
Researcher at Hitachi
Publications - 82
Citations - 1525
Ryoichi Hori is an academic researcher from Hitachi. The author has contributed to research in topics: Semiconductor memory & Dynamic random-access memory. The author has an hindex of 24, co-authored 82 publications receiving 1521 citations.
Papers
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Patent
Semiconductor memory device and defect remedying method thereof
Kazuhiko Kajigaya,Kazuyuki Miyazawa,Manabu Tsunozaki,Kazuyoshi Oshima,Takashi Yamazaki,Yuji Sakai,Jiro Sawada,Yasunori Yamaguchi,Tetsurou Matsumoto,Shinji Udo,Yoshioka Hiroshi,Hirokazu Saito,Mitsuhiro Takano,Makoto Morino,Sinichi Miyatake,Eiji Miyamoto,Yasuhiro Kasama,Akira Endo,Ryoichi Hori,Jun Etoh,Masashi Horiguchi,Shinichi Ikenaga,Atsushi Kumata +22 more
TL;DR: In this paper, the authors proposed a cross-area memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions.
Patent
Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions
TL;DR: In this paper, a semiconductor integrated circuit (SIC) consists of a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on a chip, and a control circuit on the chip for controlling the power supply circuit.
Patent
Semiconductor circuit with low power consumption having emitter-coupled logic or differential amplifier
Goro Kitsukawa,Kazumasa Yanagisawa,Takayuki Kawahara,Ryoichi Hori,Yoshinobu Nakagome,Noriyuki Hamma,Kiyoo Itoh,Hiromi Tukada +7 more
TL;DR: In this article, a current switch and an emitter follower are coupled to reduce the power consumption of the ECL circuit and suppress fluctuations in the voltage levels of the outputs of the output of the current switch.
Patent
Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement
Toshiyuki Sakuta,Masamichi Ishihara,Kazuyuki Miyazawa,Masanori Tazunoki,Hidetoshi Iwai,Hisashi Nakamura,Yasushi Takahashi,Toshio Maeda,Hiromi Matsuura,Ryoichi Hori,Toshio Sasaki,Osamu Sakai,Hiroyuki Uchiyama,Eiji Miyamoto,Kazuyoshi Oshima,Yasuhiro Kasama +15 more
TL;DR: In this paper, a semiconductor integrated circuit memory structure is provided which uses macro-cellulated circuit blocks that can permit a very large storage capability (for example, on the order of 64 Mbits in a DRAM) on a single chip.
Journal ArticleDOI
A 5 V-only 64K dynamic RAM based on high S/N design
TL;DR: A 5 V-only 64K dynamic RAM is designed and fabricated using double poly-Si technology based on the 3 /spl mu/m design rule, with a typical access time of 120 ns and a 170 mW operating power, with minimized sense noise of less than 50 mV.