Showing papers in "IEEE Journal of Solid-state Circuits in 1980"

Electron Mobility in Inversion and Accumulation Layers on Thermally Oxidized Silicon Surfaces

Abstract: Accurate modeling of MOS devices requires quantitative knowledge of carrier mobilities in surface inversion and accumulation layers. Optimization of device structures and accurate circuit simulation, particularly as technologies push toward fundamental limits, necessitate an understanding of how impurity doping levels, oxide charge densities, process techniques, and applied electric fields affect carrier surface nobilities. It is the purpose of this paper to present an extensive set of experimental results on the behavior of electron surface mobility in thermally oxidized silicon structures. EmpiricaI equations are developed which allow the calculation of electron mobility under a wide variety of substrate, process, and electrical conditions. The experimental results are interpreted in terms of the dominant physical mechanisms responsible for mobility degradation at the Si/SiO/sub 2/ interface. From the observed effects of process parameters on mobility roll-off under high vertical fields, conclusions are drawn about optimum process conditions for maximizing mobility. The implications of this work for performance limits of several types of MOS devices are described.

The behaviour of flip-flops used as synchronizers and prediction of their failure rate

Abstract: Deals with the behavior of flip-flops, used as input synchronizers, in particular when they operate in the metastable region. It is shown first, theoretically as well as experimentally, that the average rate of system failures, due to the occurrence of metastable states (MSSs), is independent of circuit noise. A formula which describes the probability of occurrence of a metastable state has been derived. To verify the theory, measurements have been made on a flip-flop made in n-channel MOS technology. Also a method is given for predicting the average number of system failures, for a given flip-flop, occurring over a year. This method is applied to predict this average failure rate for the designed synchronizer.

Accurate analysis of temperature effects in I/SUB c/V/SUB BE/ characteristics with application to bandgap reference sources

Abstract: The inaccuracy of the analyses commonly used for predicting the temperature behavior of the I/SUB C/-V/SUB BE/ characteristics of transistors and the output of bandgap reference sources is pointed out. The problem is traced to a basic assumption implicit in such analyses, namely that the variation of the bandgap voltage of silicon with temperature is linear; this assumption is shown to be of poor accuracy. By taking into account the nonlinearity in this variation, new accurate formulas are derived. Both the previous analyses and the proposed analysis are compared to experiment; a valuable improvement is demonstrated. Equations which should prove to value in the design of bandgap reference sources and bipolar transistor temperatures transducers are given. Higher order effects are discussed.

Built-in test for complex digital integrated circuits

Abstract: A method for testing the logic function of complex digital integrated circuits is presented. The extra hardware needed is kept minimal by functional conversion of already existing components (e.g., registers). The feasibility of the proposed method is demonstrated by results from both hardware simulation and logic simulation. The method is based on an adapted version of signature analysis, and on circuit partitioning (the structure of VLSI circuits is assumed to be inherently modular).

Transient Analysis of MOS Transistors

Abstract: Two methods have been developed for analyzing MOS transients. One method is analytical and uses the quasi-static approximation. It is useful when the stray capacitance dominates MOS transient performance. The second method is numericaf and uses a new boundary value method which can be applied over a wide range of operating speeds. This method includes secondary effects and nonuniform doping. The validity and Iimits for both methods are verified by comparison with measurements. Transit-time delay and charge-pumping effects are also analyzed using the numerical method. Examples of short-channel behavior of MOS devices are included.

Response of a correlated double sampling circuit to 1/f noise [generated in CCD arrays]

Abstract: Correlated double sampling (CDS) was introduced by White et al. (1974) as a technique for removal of switching transients and elimination of the Nyquist (reset) noise, both of which are associated with charge sensing circuits employed in charge-coupled device arrays. An additional advantage is the attenuation of the 1/f noise component in the charge sensing circuits due to the zero in the CDS noise transfer function at the origin (/spl omega/=0). The effect of the CDS circuit on the reset noise and Johnson-Nyquist (white) noise in the associated circuitry has been adequately described (see ibid., vol.SC-11, no.1, p.147, 1976). The author presents an analysis of the effect of the CDS circuit on the 1/f noise component generated in the preceding CCD circuitry.

Dynamic CMOS amplifiers

Abstract: A family of dynamic CMOS amplifiers is presented and discussed. First, the concept of dynamic circuit is introduced. Then two groups of circuits with different biasing principles are shown, and experimental results are presented. The advantages of dynamic amplifiers are low power consumption, high voltage gain, large bandwidth, and low offset voltages.

A high performance low power CMOS channel filter

Abstract: A new CMOS PCM channel filter is described, which includes transmit and receive filters on a single die. This chip displays an idle-channel noise of typically 0 dBrnC0, a power supply rejection ratio of 40-50 dB at 1 kHz, and a fully operational power dissipation of only 35 mW, making it very cost effective in telecommunication switching systems. The design of this chip, including architectural, switched capacitor filter, and amplifier considerations is described, and typical experimental results are presented.

Finite amplifier gain and bandwidth effects in switched-capacitor filters

Abstract: Discusses the effects of finite operational-amplifier gain and bandwidth on the response of the most widely used switched-capacitor filter section. Formulas are derived for the minimum acceptable values of the DC amplifier gain and the unity-gain frequency under specified conditions.

Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor

Abstract: The LDD structure, where narrow, self-aligned n/sup -/ regions are introduced between the channel and the n/sup +/ source-drain diffusions of an IGFET to spread the high field at the drain pinchoff region and thus reduce the maximum field intensity, is analyzed. The design is shown, including optimization of then- dimensions and concentrations and the boron channel doping profile and an evaluation of the effect of the series resistance of the n- regions on device transconductance. Characteristics of experimental devices are presented and compared to those of conventional IGFET's. It is shown that significant improvements in breakdown voltages, hot-electron effects, and short-channel threshold effects can be achieved allowing operation at higher voltage, e.g., 8.5 versus 5 V, with shorter source-drain spacings, e.g., 1.2 versus 1.5 /spl mu/m. Alternatively, a shorter channel length could be used for a given supply voltage. Performance projections are shown which predict 1.7 X basic device/circuit speed enhancement over conventional structures. Due to the higher voltages and higher frequency operation, the higher performance results in an increase in power which must be considered in a practical design.

MOS voltage reference based on polysilicon gate work function difference

Abstract: A voltage reference in CMOS technology is based upon transistor pairs of the same type except for the opposite doping type of their polysilicon gates. At identical drain currents, the gate voltage difference, close to the silicon bandgap, is 1.2 V/spl plusmn/0.06 V. Circuits for a positive and for a negative voltage reference are presented. Digital voltage tuning improves accuracy. Temperature compensation is provided by proper choice of current ratio or by means of an auxiliary circuit. Voltage drift is about 300 ppm//spl deg/C without compensation, and can be reduced to /spl plusmn/30 ppm//spl deg/C. The circuits work with a supply voltage of 2-10 V and draw a current that is less than 1 /spl mu/A.

A Dense Gate Matrix Layout Method for MOS VLSI

Abstract: A rapid and systematic method for performing chip layout of VLSI circuits is described. This method utilizes the configuration of a matrix composed of interacting rows and columns to provide transistor placement and interconnections. This structure, which is orderly and regular, gives high device-packing density and allows ease of checking for layout errors. Resulting layouts may be updated to new design rules automatically. This method has been used in the layout of a 20 000-transistor section of a VLSI circuit.

A 5 V-only 64K dynamic RAM based on high S/N design

Abstract: A 5 V-only 64K dynamic RAM is designed and fabricated using double poly-Si technology based on the 3 /spl mu/m design rule. The design features of this dynamic RAM are described. In particular, memory cell and S/N (signal/noise) designs are focused of a dynamic RAM with an on-chip bias generator. The device fabricated provides a typical access time of 120 ns and a 170 mW operating power, with minimized sense noise of less than 50 mV.

Practical implementation of a general computer aided design technique for switched capacitor circuits

Abstract: A general and efficient CAD method for simulation of switched capacitor filters and A/D and D/A converters, is demonstrated. It is based on the direct implementation of controlled switch branches into the widely used modified nodal analysis technique and is therefore in contrast to other methods, directly compatible with existing CAD techniques. It allows for DC, time domain, and frequency response calculations for arbitrary clock cycles and all types of inputs (piecewise constant, sample and hold, and continuous). The circuit can also contain resistors and allows for nonlinear time domain analysis too. As implemented in the Diana program it allows for full top-down design from principle to transistor level, including clock drivers, control logic, etc. Input is directly from the circuit diagram. The method is illustrated by practical design examples.

Refractory Silicides of Titanium and Tantalum for Low-Resistivity Gates and Interconnects

Abstract: A study of the refractory-gate metallization schemes had been undertaken to provide a low-resistivity metallization for LSI and VLSI. In this paper, we describe an overview of the efforts made in this direction and present two different metallization schemes which lead to a resistivity of <=20 and 40 /spl mu//spl Omega/spl dot/cm at the gate level. These schemes involve formation of titanium and tantalum silicides on polysilicon gates, respectively. The recommended structure ia a metal or a cosputtered alloy/polysilicon/gate oxide/substrate which, when sintered, gives the desired structure silicide/polysilicon/gate oxide substrate. By the use of 1000-/spl aring/ Ti or Ta, the sheet resistance of nearly 1 or 2 Omega//spl square/, respectively, can be routinely obtained. The silicides are mechanically strong and can be dry etched using radial-flow or barrel-type plasma reactors. The Ta silicide structure is found to be very stable throughout standard processing and can be retrofitted in the present processing sequence. Ti silicide structures are similarly stable except for the reactivity of the silicide with HF-containing reagents. The Ti silicide metallization scheme can therefore be employed in processing with changes incorporated to avoid HF-silicide contact.

The use of current amplifiers for high performance voltage applications

Abstract: A current amplifier is used to realize a voltage amplifier having an improved high frequency response and slew rate capability. It is shown that the closed loop bandwidth is independent of the closed loop voltage gain. The design and application of a unity gain and a high gain current amplifier to voltage signal processing circuits are given. The results demonstrate an efficient use of the inherent frequency response capabilities of the active devices in the circuit to achieve the amplification of high frequency and large amplitude voltage signals.

MINIMOS - A Two-Dimensional MOS Transistor Analyzer

Abstract: We describe a user-oriented software tool-MINIMOS-for the two-dimensional numerical simulation of planar MOS transistors. The fundamental semiconductor equations are solved with sophisticated programming techniques to allow very low computer costs. The program is able to calculate the doping profiles from the technological parameters specified by the user. A new mobility model has been implemented which takes into account the dependence on the impurity concentration, electric field, temperature, and especially the distance to the Si-SiO/sub 2/ interface. The power of the program is shown by calculating the two-dimensional internal behavior of three MOST's with 1-/spl mu/m gate length differing in respect to the ion-implantation steps. In this way, the threshold voltage shift by a shallow implantation and the suppression of punch through by a deep implantation are demonstrated. By calculating the output characteristics without and with mobile reduction, the essential influence of this effect is shown. From the sub-threshold characteristics, the suppression of short-channel effects by ion implantation becomes apparent. The MINIMOS program is available for everyone for just the handling costs.

A true logarithmic amplifier for radar IF applications

Abstract: There are certain radar receivers where the settling time of an AGC loop is unacceptable and an amplifier is required which will compress the dynamic range instantaneously. A common technique for accomplishing this is to use a logarithmic amplifier. This has other advantages in radar applications in that a logarithmic amplifier can assist in separating wanted signals from unwanted signals known as `clutter' caused by unwanted targets such as raindrops. In systems such as MTI radar systems, where it is required to detect moving targets, the phase information is important hence the logarithmic output must be at the IF frequency. In order to preserve the phase information the phase shift or delay through the log amplifier should not vary with input signal level. This type of amplifier is known as a true logarithmic amplifier. The device described in this paper is capable of producing a true logarithmic amplifier with phase matching of /spl plusmn/4/spl deg/ over an 80 dB input dynamic range at 70 MHz.

Analysis and characterization of the depletion-mode IGFET

Abstract: Using simple charge-voltage relationships, a four-terminal model is developed for the depletion-mode IGFET. Various conditions which can coexist at the surface, such as accumulation, depletion, and inversion, are taken into account. The implanted channel is approximated by a box profile. The basic model elements, namely, the source-drain transport current and the various charging currents, are explicitly given in terms of known processing data and implanted channel parameters. Device threshold voltage, drain saturation voltage, and conditions for surface inversion are explicitly given as a function of these parameters.

Three-dimensional transient thermal simulation: application to delayed short circuit protection in power ICs

Abstract: Thermal effects may represent a limiting factor in the development of integrated circuits. As the power dissipated by integrated circuits becomes more relevant, the need increases for accurate modeling of the stationary and transient thermal behavior of the die-package structure. An analytical solution of the three-dimensional transient thermal diffusion problem is presented for a two-layer structure, together with a simple computer program for the calculation of the solution. The program, implemented on a minicomputer, is proven to be fast and accurate. The simulation technique is then applied to the design of a new short-circuit protection of a 6A current booster.

A CORDIC Arithmetic Processor Chip

Abstract: A monolithic processor computes products, quotients, and several common transcendental functions. The algorithms are based on the well-known principles of "CORDIC," but recourse to a subtle novel corollary results in a scale factor of unity. Compared to older machines, the overhead burden is significantly reduced. Also, expansion of the functional repertoire beyond the circular domain, i.e., addition to the menu of hyperbolic and linear operations, is a relatively trivial matter, in terms of both hardware cost and execution time. A bulk CMOS technology with conservative layout rules is used for the sake of high reliability, low-power consumption, and good cycle speed.

A fault-tolerant 256K RAM fabricated with molybdenum-polysilicon technology

Abstract: Describes a 256K molybdenum-polysilicon (Mo-poly) gate dynamic MOS RAM using a single transistor cell. Circuit technologies, including a capacitive-coupled sense-refresh amplifier and a redundant circuitry, enable the achievement of high performance in combination with Mo-poly technology. Electron-beam direct writing and dry etching technologies are fully utilized to make 1 /spl mu/m accurate patterns. The 256K word/spl times/1 bit device is fabricated on a 5.83 mm/spl times/5.90 mm chip. Cell size is 8.05 /spl mu/m/spl times/8.60 /spl mu/m. The additional 4K spare cells and the associated circuits, in which newly developed electrically programmable elements are used, occupy less than 10 percent of the whole chip area. The measured access time is 160 ns under V/SUB DD/=5 V condition.

Design Considerations for Single-Chip Computers of the Future

Abstract: In the mid 1980's it will be possible to put a million devices (transistors or active MOS gate electrodes) onto a single silicon chip. General trends in the evolution of silicon integrated circuits are reviewed and design constraints for emeging VLSI circuits are analyzed. Desirable architectural features in modem computers are then discussed and consequences for an implementation with large-scale integrated circuits are investigated. The resulting recommended processor design includes features such as an on-chip memory hierarchy, multiple homogeneous caches for enhanced execution parallelism, support for complex data structures and high-level languages, a flexible instruction set, and communication hardware. It is concluded that a viable modular building block for the next generation of computing systems will be a self-contained computer on a single chip. A tentative allocation of the one million transistors to the various functional blocks is given, and the result is a memory intensive design.

Unified field-effect transistor theory including velocity saturation

Abstract: It is shown that in any kind of field-effect transistor structure, the usual gradual channel approximation solutions developed for v=/spl mu//SUB 0/E also hold in a slightly modified form for v=/spl mu//SUB 0/E/|1+(/spl mu//SUB 0/E/v/SUB s/)| which gives a good approximation to the velocity field relationship in silicon FETs.

Function testing of bipolar ICs and LSIs with the stroboscopic scanning electron microscope

Abstract: The functional testing of individual circuits is essential for device manufacturers when integrated circuits have not satisfied design specifications. What is required for the functional testing of modern high-density and fast IC and large scale integration (LSI) circuits is a method which has a time resolution in the subnanosecond region and a spatial resolution in the submicrometer region. Furthermore, the test probe must be easy to position on the circuit, and inspection should be possible without having to remove the passivation glass oxide. The authors show that all of these requirements can be satisfied by using a scanning electron microscope (SEM) in the stroboscopic voltage contrast mode. A microcomputer-controlled SEM allows the testing of internal circuit operations with a time resolution of 0.2 ns, a spatial resolution of 0.2 /spl mu/m, and a voltage resolution of 50 mV. Application to a bipolar hex-inverter IC, a quadruple-multiplexer IC, and a 1024 bit PROM in the megahertz region is reported to demonstrate the efficiency of the system.

An eight-channel 8 bit microprocessor compatible NMOS D/A converter with programmable scaling

Abstract: A single-chip multiple-channel D/A converter is described. The NMOS chip contains a combination of digital and analog functions. Eight output channels with 8 bit accuracy are provided and each channel has programmable end points. The values for the data and the end points are stored in an internal RAM. Sample and-hold functions are completely on-chip. Only one multiplexed opamp is required for the analog functions. The entire control logic is incorporated in an easily testable PLA. The active chip area is 8 mm/SUP 2/. There are three power supplies (15,5,-5) with a total power dissipation of 120 mW. Updating of the eight channels occurs at a 16 kHz rate (5 MHz clock). The circuit aims at applications in microprocessor driven control systems in the industrial and consumer products field.

MOS crystal oscillator design

Abstract: The operation of MOS crystal oscillators is investigated assuming near-sinusoidal AC voltages at gate and drain. It is shown that the circuit operation depends basically on only two normalized parameters. Computer solution is used to produce a series of normalized curves allowing oscillator design for prescribed start-up conditions, steady-state amplitude, and operating current. The theoretical predictions agree closely with measurements on sample circuits.

A process-insensitive high-performance NMOS operational amplifier

Abstract: A new high-performance NMOS operational amplifier is described which has been fabricated using a standard n-channel enhancement-depletion MOS process. A new input stage, employing common-mode feedback, is presented that reduces the circuit's sensitivity to process variations. The compensation of MOS cascade stages is examined and a simple improvement is shown to dramatically reduce the total compensation capacitance. It is shown that the high-performance of this design is maintained for a large variation in depletion device thresholds. Finally, an output stage is described with low quiescent power dissipation and improved driving capabilities.

An on-chip back-bias generator for MOS dynamic memory

Abstract: An on-chip back-bias generator for 64K dynamic MOS RAM has been developed.The use of this generator achieves the goal of a single 5 V power supply part while preserving the advantages of substrate bias in n-channel MOS technology. These advantages include the elimination of substrate injection current from localized forward biasing of diodes, improved speed and power characteristics, and a larger differential data signal on the bit sense lines. The generator circuit avoids several pit-falls on on-chip V/SUB BB/ generation. The circuit pumps to a known regulated voltage. This avoids substrate drift with changes in substrate current resulting from changes in cycle time. This drift will change device characteristics and degrade storage levels. A unique two-level reference scheme avoids changes in substrate bias voltage that otherwise result from the shift in V/SUB BB/ between precharged and active memory states when memory duty cycle changes. The standby power used by the generator is only 0.74 mW.

A 16 kbit electrically erasable PROM using n-channel Si-gate MNOS technology

Abstract: A 16 kbit high performance EEPROM (electrically erasable PROM) is developed using n-channel Si-gate MNOS technology. The memory cell consists of an MNOS transistor and an addressing transistor connected in series. This cell structure and advanced processing technologies, including high temperature hydrogen anneal, realize high speed, high packing density, long data retention, and no read cycle limitations when compared to conventional p-channel Al-gate MNOS memories. The 16 kbit chip shows improved features: fast access time of 140 ns, fast program time of 1 ms, fast erase time of 100 ms, and low power dissipation of 210 mW. New high voltage devices and circuits are used to obtain high breakdown voltage, resulting in a wide margin for the program voltage supply pin. This device, fully pin-compatible with the 16 kbit EPROM (UV erasable PROM), outperforms currently used EPROMs as well as conventional MNOS memories in almost all respects.