1-V power supply high-speed low-power digital circuit technology with 0.5-/spl mu/m multithreshold-voltage CMOS (MTCMOS) is proposed. This technology features both low-threshold voltage and high-threshold voltage MOSFET's in a single LSI. The low-threshold voltage MOSFET's enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFET's suppress the stand-by leakage current during the sleep period. This technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-/spl mu/W/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSI's. To demonstrate MTCMOS's effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-/spl mu/m CMOS process. >

1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication

Al3O3 thin film growth on Si(100) using binary reaction sequence chemistry

Scaling and power reduction trends in future technologies will cause subthreshold leakage currents to become an increasingly large component of total power dissipation This paper presents several dual-threshold voltage techniques for reducing standby power dissipation while still maintaining high performance in static and dynamic combinational logic blocks MTCMOS sleep transistor sizing issues are addressed, and a hierarchical sizing methodology based on mutual exclusive discharge patterns is presented A dual-V/sub t/ domino logic style that provides the performance equivalent of a purely low-V/sub t/ design with the standby leakage characteristic of a purely high-V/sub t/ implementation is also proposed

Dual-threshold voltage techniques for low-power digital circuits

A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Nonvolatile Semiconductor Memory Device

A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.

Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions

Analytical expressions are presented for subthreshold current reduction in a decoded-driver by self-reverse biasing, which is inherently required for low-voltage, low-power, high-speed DRAM's for portable equipment. The scheme involves inserting a switching MOS transistor between the driver circuits and its power supply line. The subthreshold current of the decoded-driver is reduced to the order of 10/sup -3/ in the practical temperature range (250-350 K) with 254 mV of self-reverse biasing voltage, while the delay time is only 3% more than in conventional schemes. The transition time of 1 ms from the operating state to the low subthreshold current state is sufficient to reduce the subthreshold current. The rapid recovery time of 1 ns from the low subthreshold current state does not interrupt the start of normal operation. The subthreshold current reduction was confirmed experimentally using a test chip fabricated with 0.25- mu m technology. >

Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs)

Disclosed is a one-chip ULSI which can carry out fixed operations for a wide range of power supply voltages (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which provides a fixed internal voltage for a wide range of power supply voltages, an input/output buffer which can be adapted to several input/out interface levels, a dynamic or volatile RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.

Large scale integrated circuit for low voltage operation

Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply voltage, an input/output buffer which can be adapted to several input/output levels, a dynamid RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.

Large scale integrated circuit with sense amplifier circuits for low voltage operation

Power dissipation in dynamic random-access memories (DRAM's) is described. Power reduction techniques are summarized and a comparison is made of NMOS and CMOS for individual circuits focusing on power dissipation for full- V/sub cc/ precharge and half- V/sub cc/ precharge, decoder, and clock generator. These results are then applied to actual 1-Mbit chips. The CMOS approach with a half-V/sub cc/ precharge is found to result in a power dissipation of just half that for NMOS, which is, verified through experiments on 1-Mbit CMOS and NMOS chips. Furthermore, from estimating power dissipation for DRAM chips larger than 1 Mbit, it is thought that the critical point for power-supply transition from the existing 5 V is around the 16-Mbit level.

Yoshiki Kawajiri

Papers

Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions

Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs)

Large scale integrated circuit for low voltage operation

Large scale integrated circuit with sense amplifier circuits for low voltage operation

Power Reduction Techniques in Megabit DRAM's