Spin–orbit coupling (SOC) describes the relativistic interaction between the spin and momentum degrees of freedom of electrons, and is central to the rich phenomena observed in condensed matter systems. In recent years, new phases of matter have emerged from the interplay between SOC and low dimensionality, such as chiral spin textures and spin-polarized surface and interface states. These low-dimensional SOC-based realizations are typically robust and can be exploited at room temperature. Here we discuss SOC as a means of producing such fundamentally new physical phenomena in thin films and heterostructures. We put into context the technological promise of these material classes for developing spin-based device applications at room temperature. The interplay between spin–orbit coupling and two-dimensionality has led to the emergence of new phases of matter, such as spin-polarized surface states in topological insulators, interfacial chiral spin interactions, and magnetic skyrmions in thin films, with great potential for spin-based devices. Substantial progress in the past decade in the fabrication and modelling of atomically precise interfaces and surfaces has led to the discovery of many electronic effects that are of interest for practical devices with novel functionalities. Christos Panagopoulos and colleagues review various such effects—and their technological potential—with a focus on the role of spin–orbit coupling, the fundamental interaction between the spin and charge degrees of freedom of an electron. Spin–orbit coupling can affect the electronic properties of materials at reduced dimensions, and the authors discuss the basic principles for understanding and engineering interfaces and surfaces in which spin–orbit coupling is harnessed. Examples are structures based on topological insulators where spin currents are generated or converted and magnetic layers where spin–orbit coupling leads to spin textures that can be controlled.

https://dr.ntu.edu.sg/bitstream/10356/82494/1/Emergent%20phenomena%20induced%20by%20spin%e2%80%93orbit%20coupling%20at%20surfaces%20and%20interfaces.pdf

Emergent phenomena induced by spin–orbit coupling at surfaces and interfaces

Perpendicularly magnetized materials have attracted significant interest owing to their high anisotropy, which gives rise to extremely narrow, nanosized domain walls. As a result, the recently studied current-induced domain wall motion (CIDWM) in these materials promises to enable a new class of data, memory and logic devices1, 2, 3, 4, 5. Here we propose the spin Hall effect as an alternative mechanism for CIDWM. We are able to carefully tune the net spin Hall current in depinning experiments on Pt/Co/Pt nanowires, offering unique control over CIDWM. Furthermore, we determine that the depinning efficiency is intimately related to the internal structure of the domain wall, which we control by the application of small fields along the nanowire. This manifestation of CIDWM offers an attractive degree of freedom for manipulating domain wall motion by charge currents, and sheds light on the existence of contradicting reports on CIDWM in perpendicularly magnetized materials6, 7, 8, 9, 10, 11.

/pdf/domain-wall-depinning-governed-by-the-spin-hall-effect-2sno3u443h.pdf

Domain wall depinning governed by the spin Hall effect

In this paper, recent developments in magnetic tunnel junctions (MTJs) are reported with their potential impacts on integrated circuits. MTJs consist of two metal ferromagnets separated by a thin insulator and exhibit two resistances, low (Rp) or high (Rap) depending on the relative direction of ferromagnet magnetizations, parallel (P) or antiparallel (AP), respectively. Tunnel magnetoresistance (TMR) ratios, defined as (Rap $Rp)/Rp as high as 361%, have been obtained in MTJs with Co40Fe40B20 fixed and free layers made by sputtering with an industry-standard exchange-bias structure and post deposition annealing at Ta = 400 degC. The corresponding output voltage swing DeltaV is over 500 mV, which is five times greater than that of the conventional amorphous Al-O-barrier MTJs. The highest TMR ratio obtained so far is 500% in a pseudospin-valve MTJ annealed at Ta = 475 degC, showing a high potential of the current material system. In addition to this high-output voltage swing, current-induced magnetization switching (CIMS) takes place at the critical current densities (JCO) on the order of 106 A/cm2 in these MgO-barrier MTJs. Furthermore, high antiferromagnetic coupling between the two CoFeB layers in a synthetic ferrimagnetic free layer has been shown to result in a high thermal-stability factor with a reduced JCO compared to single free-layer MTJs. The high TMR ratio enabled by the MgO-barrier MTJs, together with the demonstration of CIMS at a low JCO, allows development of not only scalable magnetoresistive random-access memory with feature sizes below 90 nm but also new memory-in-logic CMOS circuits that can overcome a number of bottlenecks in the current integrated-circuit architecture

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Magnetic Tunnel Junctions for Spintronic Memories and Beyond

This tutorial introduces the basics of emerging nonvolatile memory (NVM) technologies including spin-transfer-torque magnetic random access memory (STTMRAM), phase-change random access memory (PCRAM), and resistive random access memory (RRAM). Emerging NVM cell characteristics are summarized, and device-level engineering trends are discussed. Emerging NVM array architectures are introduced, including the onetransistor?one-resistor (1T1R) array and the cross-point array with selectors. Design challenges such as scaling the write current and minimizing the sneak path current in cross-point array are analyzed. Recent progress on megabit-to gigabit-level prototype chip demonstrations is summarized. Finally, the prospective applications of emerging NVM are discussed, ranging from the last-level cache to the storage-class memory in the memory hierarchy. Topics of three-dimensional (3D) integration and radiation-hard NVM are discussed. Novel applications beyond the conventional memory applications are also surveyed, including physical unclonable function for hardware security, reconfigurable routing switch for field-programmable gate array (FPGA), logic-in-memory and nonvolatile cache/register/flip-flop for nonvolatile processor, and synaptic device for neuro-inspired computing.

Emerging Memory Technologies: Recent Trends and Prospects

Spin-transfer torque magnetic random access memory (STT-MRAM) is a novel, magnetic memory technology that leverages the base platform established by an existing 100pnm node memory product called MRAM to enable a scalable nonvolatile memory solution for advanced process nodes. STT-MRAM features fast read and write times, small cell sizes of 6F2 and potentially even smaller, and compatibility with existing DRAM and SRAM architecture with relatively small associated cost added. STT-MRAM is essentially a magnetic multilayer resistive element cell that is fabricated as an additional metal layer on top of conventional CMOS access transistors. In this review we give an overview of the existing STT-MRAM technologies currently in research and development across the world, as well as some specific discussion of results obtained at Grandis and with our foundry partners. We will show that in-plane STT-MRAM technology, particularly the DMTJ design, is a mature technology that meets all conventional requirements for an STT-MRAM cell to be a nonvolatile solution matching DRAM and/or SRAM drive circuitry. Exciting recent developments in perpendicular STT-MRAM also indicate that this type of STT-MRAM technology may reach maturity faster than expected, allowing even smaller cell size and product introduction at smaller nodes.

Spin-transfer torque magnetic random access memory (STT-MRAM)

This paper presents a new nonvolatile magnetic flip-flop (MFF) for standby-power-critical applications. An MFF primitive cell for design libraries has been developed using 150 nm, 1.5 V CMOS and 240 nm MRAM processes. It has advantages over other nonvolatile flip-flops in high-speed store operations without endurance limitations. It also has high design compatibility with conventional CMOS LSI designs because it does not include any additional power lines and special transistors. A toggle frequency of 3.5 GHz was achieved by a SPICE simulation, which is comparable to that of a normal CMOS DFF in the same generation. The maximum frequency in a store operation was also estimated to be 500 MHz with 1-ns current width for the data backup. An MFF test chip, which includes 16-stage 8-bit shift register using MFFs, was fabricated with these processes. A 333 MHz store operation was measured without failed bits. The functional performance was sufficiently high to demonstrate the potential of MFFs, which helps to reduce the power dissipation of systems on chips (SoCs) dramatically.

Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs

We have developed a new magnetic random access memory with current-induced domain wall (DW) motion (DW-motion MRAM). We confirmed its potential of 0.1-mA and 2-ns writing with sufficient thermal stability. The obtained properties indicate that this MRAM can replace conventional high-speed embedded memories.

Low-current perpendicular domain wall motion cell for scalable high-speed MRAM

Recently there has been increased demand for not only ultra-low power, but also high performance, even in standby-power-critical applications. Sensor nodes, for example, need a microcontroller unit (MCU) that has the ability to process signals and compress data immediately. A previously reported 130nm CMOS and FeRAM-based MCU features zero-standby power and fast wakeup operation by incorporating FeRAM devices into logic circuits [1]. The 8MHz speed, however, was not sufficiently high to meet application requirements, and the FeRAM process also has drawbacks: low compatibility with standard CMOS, and write endurance limitations. A spintronics-based nonvolatile integrated circuit is a promising option to achieve zero standby power and high-speed operation, along with compatibility with CMOS processes. In this work, we demonstrate a fully nonvolatile 16b MCU using 90nm standard CMOS and three-terminal SpinRAM technology. It achieves 20MHz, 145μW/MHz operation with a 1V supply in the active state, and 4.5μW intermittent operation with 120ns wakeup time and 0.1% active ratio, without forwarding of re-boot code from memory. The features provide sufficiently long battery life to achieve maintenance-free sensor nodes.

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications

Since MRAM cells have unlimited write endurance, they can be used as substitutes for DRAMs or SRAMs. MRAMs in electronic appliances enhance their convenience and energy efficiency because data in MRAMs are nonvolatile and retained even in the power-off state. Therefore, 2 to 16Mb standalone MRAMs have been developed [1–4]. However, in terms of their random-access times, they are not enough fast (25ns) [1] as substitutes for all kinds of stand-alone DRAMs or SRAMs. To attain a standalone MRAM with both a fast random-access time and a large capacity, we adopt a cell structure with 2 transistors and 1 magnetic tunneling junction (2T1MTJ), which we previously published for a 1Mb embedded MRAM macro [5]. We need to develop circuit schemes to achieve a larger memory capacity and a higher cell-occupation ratio with small access-time degradation. We describe the circuit schemes of a 32Mb MRAM, which enable 63% cell occupation ratio and 12ns access time.

A 90nm 12ns 32Mb 2T1MTJ MRAM

A nonvolatile magnetic flip-flop (MFF) primitive cell for SoC design libraries has been developed using a unique MRAM process. It has high design compatibility with conventional CMOS LSI designs. MFF maximum frequency was estimated to be 3.5 GHz, which is comparable to that of a normal CMOS DFF. An MFF test chip was fabricated with the process. The chippsilas functional performance was sufficiently high to demonstrate the potential of MFFs, which helps to reduce the power dissipation of SoCs dramatically.

Ryusuke Nebashi

Papers

Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs

Low-current perpendicular domain wall motion cell for scalable high-speed MRAM

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications

A 90nm 12ns 32Mb 2T1MTJ MRAM

Nonvolatile Magnetic Flip-Flop for standby-power-free SoCs