Magnetic tunnel junctions (MTJs) with ferromagnetic electrodes possessing a perpendicular magnetic easy axis are of great interest as they have a potential for realizing next-generation high-density non-volatile memory and logic chips with high thermal stability and low critical current for current-induced magnetization switching. To attain perpendicular anisotropy, a number of material systems have been explored as electrodes, which include rare-earth/transition-metal alloys, L1(0)-ordered (Co, Fe)-Pt alloys and Co/(Pd, Pt) multilayers. However, none of them so far satisfy high thermal stability at reduced dimension, low-current current-induced magnetization switching and high tunnel magnetoresistance ratio all at the same time. Here, we use interfacial perpendicular anisotropy between the ferromagnetic electrodes and the tunnel barrier of the MTJ by employing the material combination of CoFeB-MgO, a system widely adopted to produce a giant tunnel magnetoresistance ratio in MTJs with in-plane anisotropy. This approach requires no material other than those used in conventional in-plane-anisotropy MTJs. The perpendicular MTJs consisting of Ta/CoFeB/MgO/CoFeB/Ta show a high tunnel magnetoresistance ratio, over 120%, high thermal stability at dimension as low as 40 nm diameter and a low switching current of 49 microA.

A perpendicular-anisotropy CoFeB–MgO magnetic tunnel junction

The authors of the International Technology Roadmap for Semiconductors-the industry consensus set of goals established for advancing silicon integrated circuit technology-have challenged the computing research community to find new physical state variables (other than charge or voltage), new devices, and new architectures that offer memory and logic functions beyond those available with standard transistors. Recently, ultra-dense resistive memory arrays built from various two-terminal semiconductor or insulator thin film devices have been demonstrated. Among these, bipolar voltage-actuated switches have been identified as physical realizations of 'memristors' or memristive devices, combining the electrical properties of a memory element and a resistor. Such devices were first hypothesized by Chua in 1971 (ref. 15), and are characterized by one or more state variables that define the resistance of the switch depending upon its voltage history. Here we show that this family of nonlinear dynamical memory devices can also be used for logic operations: we demonstrate that they can execute material implication (IMP), which is a fundamental Boolean logic operation on two variables p and q such that pIMPq is equivalent to (NOTp)ORq. Incorporated within an appropriate circuit, memristive switches can thus perform 'stateful' logic operations for which the same devices serve simultaneously as gates (logic) and latches (memory) that use resistance instead of voltage or charge as the physical state variable.

‘Memristive’ switches enable ‘stateful’ logic operations via material implication

The authors observed tunnel magnetoresistance (TMR) ratio of 604% at 300K in Ta∕Co20Fe60B20∕MgO∕Co20Fe60B20∕Ta pseudo-spin-valve magnetic tunnel junction annealed at 525°C. To obtain high TMR ratio, it was found critical to anneal the structure at high temperature above 500°C, while suppressing the Ta diffusion into CoFeB electrodes and in particular to the CoFeB∕MgO interface. X-ray diffraction measurement of MgO on SiO2 or Co20Fe60B20 shows that an improvement of MgO barrier quality, in terms of the degree of the (001) orientation and stress relaxation, takes place at annealing temperatures above 450°C. The highest TMR ratio observed at 5K was 1144%.

/pdf/tunnel-magnetoresistance-of-604-at-300k-by-suppression-of-ta-2yiy65l5s3.pdf

Tunnel magnetoresistance of 604% at 300K by suppression of Ta diffusion in CoFeB∕MgO∕CoFeB pseudo-spin-valves annealed at high temperature

The magnetization of a magnetic material can be reversed by using electric currents that transport spin angular momentum. In the reciprocal process a changing magnetization orientation produces currents that transport spin angular momentum. Understanding how these processes occur reveals the intricate connection between magnetization and spin transport, and can transform technologies that generate, store or process information via the magnetization direction. Here we explain how currents can generate torques that affect the magnetic orientation and the reciprocal effect in a wide variety of magnetic materials and structures. We also discuss recent state-of-the-art demonstrations of current-induced torque devices that show great promise for enhancing the functionality of semiconductor devices.

https://physics.nyu.edu/kentlab/Papers/2012/NatureMaterials_11_372_2012.pdf

Current-induced torques in magnetic materials

Neurons in the brain behave as nonlinear oscillators, which develop rhythmic activity and interact to process information. Taking inspiration from this behaviour to realize high-density, low-power neuromorphic computing will require very large numbers of nanoscale nonlinear oscillators. A simple estimation indicates that to fit 108 oscillators organized in a two-dimensional array inside a chip the size of a thumb, the lateral dimension of each oscillator must be smaller than one micrometre. However, nanoscale devices tend to be noisy and to lack the stability that is required to process data in a reliable way. For this reason, despite multiple theoretical proposals and several candidates, including memristive and superconducting oscillators, a proof of concept of neuromorphic computing using nanoscale oscillators has yet to be demonstrated. Here we show experimentally that a nanoscale spintronic oscillator (a magnetic tunnel junction) can be used to achieve spoken-digit recognition with an accuracy similar to that of state-of-the-art neural networks. We also determine the regime of magnetization dynamics that leads to the greatest performance. These results, combined with the ability of the spintronic oscillators to interact with each other, and their long lifetime and low energy consumption, open up a path to fast, parallel, on-chip computation based on networks of oscillators.

/pdf/neuromorphic-computing-with-nanoscale-spintronic-oscillators-3e3rewmz7x.pdf

Neuromorphic computing with nanoscale spintronic oscillators

In this paper, recent developments in magnetic tunnel junctions (MTJs) are reported with their potential impacts on integrated circuits. MTJs consist of two metal ferromagnets separated by a thin insulator and exhibit two resistances, low (Rp) or high (Rap) depending on the relative direction of ferromagnet magnetizations, parallel (P) or antiparallel (AP), respectively. Tunnel magnetoresistance (TMR) ratios, defined as (Rap $Rp)/Rp as high as 361%, have been obtained in MTJs with Co40Fe40B20 fixed and free layers made by sputtering with an industry-standard exchange-bias structure and post deposition annealing at Ta = 400 degC. The corresponding output voltage swing DeltaV is over 500 mV, which is five times greater than that of the conventional amorphous Al-O-barrier MTJs. The highest TMR ratio obtained so far is 500% in a pseudospin-valve MTJ annealed at Ta = 475 degC, showing a high potential of the current material system. In addition to this high-output voltage swing, current-induced magnetization switching (CIMS) takes place at the critical current densities (JCO) on the order of 106 A/cm2 in these MgO-barrier MTJs. Furthermore, high antiferromagnetic coupling between the two CoFeB layers in a synthetic ferrimagnetic free layer has been shown to result in a high thermal-stability factor with a reduced JCO compared to single free-layer MTJs. The high TMR ratio enabled by the MgO-barrier MTJs, together with the demonstration of CIMS at a low JCO, allows development of not only scalable magnetoresistive random-access memory with feature sizes below 90 nm but also new memory-in-logic CMOS circuits that can overcome a number of bottlenecks in the current integrated-circuit architecture

/pdf/magnetic-tunnel-junctions-for-spintronic-memories-and-beyond-2tm3rrxd78.pdf

Magnetic Tunnel Junctions for Spintronic Memories and Beyond

Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay. We have fabricated a nonvolatile full adder based on logic-in-memory architecture using magnetic tunnel junctions (MTJs) in combination with metal oxide semiconductor (MOS) transistors. Magnesium oxide (MgO) barrier MTJs are used to take advantage of their high tunnel magneto-resistance (TMR) ratio and spin-injection write capability. The MOS transistors are fabricated using a 0.18 µm complementary metal oxide semiconductor (CMOS) process. The basic operation of the full adder is confirmed.

https://iopscience.iop.org/article/10.1143/APEX.1.091301/pdf

Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions

The hardware implementation of deep neural networks (DNNs) has recently received tremendous attention: many applications in fact require high-speed operations that suit a hardware implementation. However, numerous elements and complex interconnections are usually required, leading to a large area occupation and copious power consumption. Stochastic computing (SC) has shown promising results for low-power area-efficient hardware implementations, even though existing stochastic algorithms require long streams that cause long latencies. In this paper, we propose an integer form of stochastic computation and introduce some elementary circuits. We then propose an efficient implementation of a DNN based on integral SC. The proposed architecture has been implemented on a Virtex7 field-programmable gate array, resulting in 45% and 62% average reductions in area and latency compared with the best reported architecture in the literature. We also synthesize the circuits in a 65-nm CMOS technology, and we show that the proposed integral stochastic architecture results in up to 21% reduction in energy consumption compared with the binary radix implementation at the same misclassification rate. Due to fault-tolerant nature of stochastic architectures, we also consider a quasi-synchronous implementation that yields 33% reduction in energy consumption with respect to the binary radix implementation without any compromise on performance.

VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing

The hardware implementation of deep neural networks (DNNs) has recently received tremendous attention since many applications require high-speed operations. However, numerous processing elements and complex interconnections are usually required, leading to a large area occupation and a high power consumption. Stochastic computing has shown promising results for area-efficient hardware implementations, even though existing stochastic algorithms require long streams that exhibit long latency. In this paper, we propose an integer form of stochastic computation and introduce some elementary circuits. We then propose an efficient implementation of a DNN based on integral stochastic computing. The proposed architecture uses integer stochastic streams and a modified Finite State Machine-based tanh function to improve the performance and reduce the latency compared to existing stochastic architectures for DNN. The simulation results show the negligible performance loss of the proposed integer stochastic DNN for different network sizes compared to their floating point versions.

VLSI implementation of deep neural networks using integral stochastic computing

This paper reviews emerging nonvolatile random access memories (RAM) in recent years. It first benchmarks ferroelectric RAM (FeRAM), phase change RAM (PCRAM), resistive RAM (ReRAM), and spin-torque-transfer magnetic RAM (STT-MRAM), discussing each RAM's features and its applications. Then current status of spintronics developments including not only STT-MRAM but also nonvolatile logic LSI is described, which are particularly suitable for working memory applications.

Takahiro Hanyu

Papers

Magnetic Tunnel Junctions for Spintronic Memories and Beyond

Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions

VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing

VLSI implementation of deep neural networks using integral stochastic computing

An Overview of Nonvolatile Emerging Memories— Spintronics for Working Memories