The rapid growth of the electrical modeling and analysis of the interconnect structure, both at the electronic chip and package level, can be attributed to the increasing importance of the electromagnetic properties of the interconnect circuit on the overall electrical performance of state-of-the-art very large scale integration (VLSI) systems. With switching speeds well below 1 ns in today's gigahertz processors, and VLSI circuit complexity exceeding the 100 million transistors per chip mark, power and signal distribution is characterized by multigigahertz bandwidth pulses propagating through a tightly coupled three-dimensional wiring structure that exhibits resonant behavior at the upper part of the spectrum. Consequently, in addition to the inductive and capacitive coupling, present between adjacent wires across the entire frequency bandwidth, distributed electromagnetic effects, manifested as interconnect-induced delay, reflection, radiation, and long-range nonlocal coupling, become prominent at high frequencies, with a decisive impact of overall system performance. The electromagnetic nature of such high-frequency effects, combined with the geometric complexity of the interconnect structure, make the electrical design of today's performance-driven systems extremely challenging. Its success is heavily dependent on the availability of sophisticated electromagnetic modeling methodologies and computer-aided design tools. This paper presents an overview of the different approaches employed today for the development of an electromagnetic modeling and simulation framework that can effectively tackle the complexity of the interconnect circuit and facilitate its design. In addition to identifying the current state of the art, an assessment is given of the challenges that lie ahead in the signal integrity-driven electrical design of tomorrow's performance- and/or portability-driven, multifunctional ULSI systems.

Progress in the methodologies for the electrical modeling of interconnects and electronic packages

This paper compares the major classes of chip-to-chip and on-chips interconnections used in high-performance computers and communication systems and reviews their electrical characteristics. Measurement results of dielectric loss are shown and the attenuation is compared for printed-circuit-board, glass-ceramic, thin-film, and on-chip wiring. Simulation results are shown with representative driver and receiver circuits, guidelines are given for when losses are significant, and predictions are made for the sustainable bandwidths on useful wiring lengths.

Frequency-dependent losses on high-performance interconnections

As 1999 ended, IBM announced its intention to construct a one-petaflop supercomputer. The construction of this system was based on a cellular architecture--the use of relatively small but powerful building blocks used together in sufficient quantities to construct large systems. The first step on the road to a petaflop machine (one quadrillion floating-point operations in a second) is the Blue Gene®/L supercomputer. Blue Gene/L combines a low-power processor with a highly parallel architecture to achieve unparalleled computing performance per unit volume. Implementing the Blue Gene/L packaging involved trading off considerations of cost, power, cooling, signaling, electromagnetic radiation, mechanics, component selection, cabling, reliability, service strategy, risk, and schedule. This paper describes how 1,024 dual-processor compute application-specific integrated circuits (ASICs) are packaged in a scalable rack, and how racks are combined and augmented with host computers and remote storage. The Blue Gene/L interconnect, power, cooling, and control systems are described individually and as part of the synergistic whole.

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Packaging the Blue Gene/L supercomputer

This paper analyzes methods to minimize the power-delay product of 64-bit carry-select adders intended for high-performance and low-power applications. A first realization in 0.18-/spl mu/m partially depleted (PD) silicon-on-insulator (SOI), using complex branch-based logic (BBL) cells, results in a delay of 720 ps and a power dissipation of 96 mW at 1.5 V. The reduction of the stack height in the critical path, combined with the optimization of the global carry network with cell sharing and the selection of 8-bit pre-sums, leads to a reduction of the power-delay product by 75%. The automatic tuning of the transistor widths in 0.13-/spl mu/m PD SOI produces an energy-efficient 64-bit adder which has a delay of 326 ps and a power dissipation of 23 mW only at 1.1 V.

Power-delay product minimization in high-performance 64-bit carry-select adders

Shrinking transistor sizes, increasing circuit complexities, and high clock frequencies bring new board-routing challenges that cannot be handled effectively by traditional routing algorithms. Many high-end designs in the industry today require manual routing efforts, which increases the design-cycle times considerably. In this paper, we propose an escape-routing algorithm to route nets within multiple dense components simultaneously so that the number of crossings in the intermediate area is minimized. We also show how to handle high-speed-design constraints within the framework of this algorithm. Experimental comparisons with a recently proposed algorithm show that our algorithm reduces the via requirements of industrial test cases on average by 39%.

Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards

The multichip module (MCM) that contains the central electronic complex (CEC) of the S/390 G5 system is described in this paper. The glass-ceramic module, topped with six layers of polyimide full-field thin-film wiring for chipto-chip interconnection, represents IBM’s most advanced packaging technology. This MCM provides a large wiring capacity, with 595 meters of routed interconnection; it supports the highest synchronous interconnection performance in the industry at 300 MHz; and it allows for cooling flexibility at the system level—either a heat sink for air-cooled systems or a cooling “hat” for systems using refrigeration cooling. The physical and electrical characteristics of this packaging technology, necessary to support the aggressive system performance goals (1040 MIPS) of the IBM G5 Enterprise Servers, are presented here. In addition, the approach used to produce a robust electrical and physical design is described.

MCM technology and design for the S/390 G5 system

In this paper, we describe the challenging first- and second-level packaging technology of a new system packaging architecture for the IBM eServerTM z990. The z990 dramatically increases the volumetric processor density over that of the predecessor z900 by implementing a super-blade design comprising four node cards. Each blade is plugged into a common center board, and a blade contains the node with up to sixteen processor cores on the multichip module (MCM), up to 64 GB of memory on two memory cards, and up to twelve self-timed interface (STI) cables plugged into the front of the node. Each glass-ceramic MCM carries 16 chips dissipating a maximum power of 800 W. In this super-blade design, the packaging complexity is increased dramatically over that of the previous zSeries® eServer z900 to achieve increased volumetric density, processor performance, and system scalability. This approach permits the system to be scaled from one to four nodes, with full interaction between all nodes using a ring structure for the wiring between the four nodes. The processor frequencies are increased to 1.2 GHz, with a 0.6-GHz nest with synchronous double-data-rate interchip and interblade communication. This data rate over these package connections demands an electrical verification methodology that includes all of the different relevant system components to ensure that the proper signal and power distribution operation is achieved. The signal integrity analysis verifies that crosstalk limits are not exceeded and proper timing relationships are maintained. The power integrity simulations are performed to optimize the hierarchical decoupling in order to maintain the voltage on the power distribution networks within prescribed limits.

S. A. Kuppinger

Papers

MCM technology and design for the S/390 G5 system

First- and second-level packaging of the z990 processor cage