Planar circuits for microwaves and lightwaves

Interconnecting integrated circuits (ICs) and 3-D-ICs to the system board (printed circuit board) are currently achieved using organic or silicon-based interposers. Organic interposers face several challenges in packaging 2-D and 3-D-ICs beyond the 32-nm node, primarily due to their poor dimensional stability and coefficient of thermal expansion (CTE) mismatch to silicon. Silicon interposers made with back-end of line wafer processes can achieve the required wiring and I/O density, but their high-cost limit them to high-performance applications. Glass is proposed as a superior alternative to organic and silicon-based interposers for packaging of future ICs and 3-D-ICs with highest I/Os at lowest cost. This paper presents for the first time a novel thin and large panel glass interposer capable of scaling to 700 mm and larger panels with potential for significant cost reduction over interposers made on 200-mm or 300-mm wafers. The formation of small through vias at high speed has been the biggest technical barrier for the adoption of glass as an interposer and system substrate; and this paper describes pioneering research in via-formation in thin glass substrates, using a novel “polymer-on-glass” approach. Electrical modeling and design of through package vias (TPVs) in glass is discussed in detail, and the feasibility of 50-μm pitch TPVs in 180-μm thin glass substrates has been demonstrated. The excellent surface finish and low CTE of glass leads to increased I/O density, and increased functionality per unit area leading to system miniaturization.

Low-Cost Thin Glass Interposers as a Superior Alternative to Silicon and Organic Interposers for Packaging of 3-D ICs

Interposer technology has evolved from ceramic to organic materials and most recently to silicon. Organic substrates exhibit poor dimensional stability, thus requiring large capture pads which make them unsuitable for very high I/Os with fine pitch interconnections. Therefore, there has been a trend to develop silicon interposers. Silicon interposers however, suffer in two ways; 1) they are expensive to process due to the need for electrical insulation around via walls, and 2) they are limited in size by the silicon wafer from which they originate. In this paper, glass is proposed as a superior alternative interposer technology to address the limitations of both silicon and organic interposers. The inherent electrical properties of glass, together with large area panel size availability, make it superior compared to organic and silicon-based interposers. Glass however, is not without its challenges. It suffers in two ways: 1) formation of vias at low cost, and 2) its lower thermal conductivity compared to silicon. This research explores glass as an interposer material, and addresses the above key challenges in through package via (TPV) formation and subsequent low cost and large area metallization to achieve very high I/Os at fine pitch.

Through-package-via formation and metallization of glass interposers

As 1999 ended, IBM announced its intention to construct a one-petaflop supercomputer. The construction of this system was based on a cellular architecture--the use of relatively small but powerful building blocks used together in sufficient quantities to construct large systems. The first step on the road to a petaflop machine (one quadrillion floating-point operations in a second) is the Blue Gene®/L supercomputer. Blue Gene/L combines a low-power processor with a highly parallel architecture to achieve unparalleled computing performance per unit volume. Implementing the Blue Gene/L packaging involved trading off considerations of cost, power, cooling, signaling, electromagnetic radiation, mechanics, component selection, cabling, reliability, service strategy, risk, and schedule. This paper describes how 1,024 dual-processor compute application-specific integrated circuits (ASICs) are packaged in a scalable rack, and how racks are combined and augmented with host computers and remote storage. The Blue Gene/L interconnect, power, cooling, and control systems are described individually and as part of the synergistic whole.

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Packaging the Blue Gene/L supercomputer

We present a complete workflow for the extraction of behavioral reduced-order models of wired interconnect links, including an explicit dependence on geometrical or material parameters describing internal discontinuities that may affect the quality of signal transmission. Thanks to the adopted structure, the models are easily identified from sampled frequency responses at discrete points in the parameter space. Such responses are obtained from off-the-shelf full-wave solvers. A novel algorithm is used for checking and enforcing model stability and passivity, two fundamental requirements for reliably running stable transient simulations. Finally, an ad hoc procedure is devised to synthesize the models as parameterized circuit equivalents, compatible with any SPICE solver. Several examples illustrate and validate the workflow, confirming the suitability of the proposed approach for what-if, parameter sweep, design centering, and optimization through time-domain simulations, possibly including nonlinear devices and terminations.

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Behavioral, Parameterized, and Broadband Modeling of Wired Interconnects With Internal Discontinuities

This paper presents a general strategy for the electrical performance and signal integrity assessment of electrically long multichip links. A black-box time-domain macromodel is first derived from tabulated frequency responses in scattering form. This model is structured as a combination of ideal delay terms with frequency-dependent rational coefficients. A new identification scheme is presented, which is based on an initial blind delay estimation process followed by a refinement loop based on an iterative delayed vector fitting process. Two alternative passivity enforcement schemes based on local perturbations are then presented. The result is an accurate and guaranteed passive delay-based macromodel, which is synthesized as a SPICE-compatible netlist for channel analysis. The proposed procedure enables safe and reliable circuit-based transient simulations of complex multichip links, including nonlinear drivers and receivers. The performance of the proposed flow is demonstrated on a large number of channel benchmarks.

Signal Integrity Verification of Multichip Links Using Passive Channel Macromodels

In this paper, we describe the challenging first- and second-level packaging technology of a new system packaging architecture for the IBM eServerTM z990. The z990 dramatically increases the volumetric processor density over that of the predecessor z900 by implementing a super-blade design comprising four node cards. Each blade is plugged into a common center board, and a blade contains the node with up to sixteen processor cores on the multichip module (MCM), up to 64 GB of memory on two memory cards, and up to twelve self-timed interface (STI) cables plugged into the front of the node. Each glass-ceramic MCM carries 16 chips dissipating a maximum power of 800 W. In this super-blade design, the packaging complexity is increased dramatically over that of the previous zSeries® eServer z900 to achieve increased volumetric density, processor performance, and system scalability. This approach permits the system to be scaled from one to four nodes, with full interaction between all nodes using a ring structure for the wiring between the four nodes. The processor frequencies are increased to 1.2 GHz, with a 0.6-GHz nest with synchronous double-data-rate interchip and interblade communication. This data rate over these package connections demands an electrical verification methodology that includes all of the different relevant system components to ensure that the proper signal and power distribution operation is achieved. The signal integrity analysis verifies that crosstalk limits are not exceeded and proper timing relationships are maintained. The power integrity simulations are performed to optimize the hierarchical decoupling in order to maintain the voltage on the power distribution networks within prescribed limits.

First- and second-level packaging of the z990 processor cage

IBM z13 processor drawer W. D. Becker H. Harrer A. Huber W. L. Brodsky R. Krabbenhoft M. A. Cracraft D. Kaller G. Edlund T. Strach The electronic packaging of the IBM z13i is the foundation for a processor drawer that provides a significant increase in processing power relative to the IBM zEnterpriseA EC12 (zEC12) system while managing power and cost to meet the z13 product objectives. The z13 system architecture differs from previous high-end z Systemsi designs due to the introduction of a drawer-based processor design, organic single-chip modules (SCMs) in place of the ceramic MCMs (multi-chip modules), and a cabled interconnect between drawers in place of the PCB (printed circuit board) backplane of the zEC12. These innovations are coupled with next-generation signaling interfaces, providing a significant increase in signal bandwidth. The next-generation voltage regulation and decoupling provides the efficient power delivery needed to build a new processor subsystem with 40% more processor cores than the zEC12. The memory bandwidth and capacity have more than tripled, and the input/output bandwidth of the processor chip doubled to provide excellent scalability at the processor socket, drawer, and system level. The electronic packaging has been designed to meet all of these challenges, and this paper presents the design and integration of the electronic packaging of the z13 system.

Electronic packaging of the IBM z13 processor drawer

The high dense interconnect (HDI) organic chip packaging technology has made rapid development advancements in the last few years. Due to the dense wiring structures in the build up layers and the recently introduced fine line core with micro vias, high signal input/output (I/O) applications and dense chip area array footprints can be supported. These technology improvements support specific new dense chip applications. In this paper the electrical characteristics and the evolution of this packaging technology is described. The electrical description is especially focussed on material characteristics and the signal integrity including cross talk. In addition the impact on high speed data transmission and the performance differences between single-chip module (SCM) and multichip modules (MCM) are discussed. Also the power integrity is described on the basis of the results of a mid frequency power noise analysis.

Evolution of organic chip packaging technology for high speed applications

In this paper, we describe the first- and second-level system packaging structure of the IBM zEnterprise® 196 (z196) enterprise-class server. The design point required a more than 50% overall increase in system performance (in millions of instructions per second) in comparison to its predecessor. This resulted in a new system design that includes, among other things, increased input/output bandwidth, more processors with higher frequencies, and increased current demand of more than 2,000 A for the six processor chips and two cache chips per multichip module. To achieve these targets, we implemented several new packaging technologies. The z196 enterprise-class server uses a new differential memory interface between the processor chips and custom-designed server memory modules. The electrical power delivery system design follows a substantially new approach using Vicor Factor Power® blocks, which results in higher packaging integration density and minimized package electrical losses. The power noise decoupling strategy was changed because of the availability of deep-trench technology on the new processor chip generation.

Dierk Kaller

Papers

Signal Integrity Verification of Multichip Links Using Passive Channel Macromodels

First- and second-level packaging of the z990 processor cage

Electronic packaging of the IBM z13 processor drawer

Evolution of organic chip packaging technology for high speed applications

Electronic packaging of the IBM System z196 enterprise-class server processor cage