We analyze Schmitt-Trigger (ST)-based differential-sensing static random access memory (SRAM) bitcells for ultralow-voltage operation. The ST-based SRAM bitcells address the fundamental conflicting design requirement of the read versus write operation of a conventional 6T bitcell. The ST operation gives better read-stability as well as better write-ability compared to the standard 6T bitcell. The proposed ST bitcells incorporate a built-in feedback mechanism, achieving process variation tolerance - a must for future nano-scaled technology nodes. A detailed comparison of different bitcells under iso-area condition shows that the ST-2 bitcell can operate at lower supply voltages. Measurement results on ten test-chips fabricated in 130-nm CMOS technology show that the proposed ST-2 bitcell gives 1.6× higher read static noise margin, 2× higher write-trip-point and 120-mV lower read-Vmin compared to the iso-area 6T bitcell.

Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design

This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The disturb-free feature facilitates bit-interleaving architecture, which can reduce multiple-bit upsets in a single word and enhance soft error immunity by employing Error Checking and Correction (ECC) technique. The proposed 9T SRAM cell is demonstrated by a 72 Kb SRAM macro with a Negative Bit-Line (NBL) Write-assist and an adaptive Read operation timing tracing circuit implemented in 65 nm low-leakage CMOS technology. Measured full Read and Write functionality is error free with VDD down to 0.35 V ( 0.15 V lower than the threshold voltage) with 229 KHz frequency and 4.05 μW power. Data is held down to 0.275 V with 2.29 μW Standby power. The minimum energy per operation is 4.5 pJ at 0.5 V. The 72 Kb SRAM macro has wide operation range from 1.2 V down to 0.35 V, with operating frequency of around 200 MHz for VDD around/above 1.0 V.

/pdf/a-single-ended-disturb-free-9t-subthreshold-sram-with-cross-221sd28qry.pdf

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

Since Moore’s law driven scaling of planar MOSFETs
faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing
to the presence of multiple (two/three) gates, FinFETs/Trigate
FETs are able to tackle short-channel effects (SCEs) better than
conventional planar MOSFETs at deeply scaled technology nodes
and thus enable continued transistor scaling. In this paper, we
review research on FinFETs from the bottommost device level
to the topmost architecture level. We survey different types of
FinFETs, various possible FinFET asymmetries and their impact,
and novel logic-level and architecture-level tradeoffs offered by
FinFETs. We also review analysis and optimization tools that
are available for characterizing FinFET devices, circuits, and
architectures.

/pdf/finfets-from-devices-to-architectures-3wvjf3zgcz.pdf

FinFETs: From Devices to Architectures

This paper presents a Schmitt-trigger-based single-ended 11T SRAM cell, which significantly improves read and write static noise margin (SNM) and consumes low power. Simulation results show that the cell also achieves the lowest leakage power dissipation among the cells considered for comparison. We also investigate the impact of process, voltage, and temperature variations on various performance parameters, such as hold SNM, read SNM, write margin, immunity to half-select issue, $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ ratio of read path, and leakage power of the cell; Monte Carlo simulation results confirm the robustness of the proposed cell toward these issues. Layout drawn in a 45-nm technology rule shows that the proposed cell occupies $2.02\times $ greater area as compared with 6T SRAM cells. However, $6.9\times $ higher $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ ratio of the read path of the proposed cell as compared with 6T cell holds potential to significantly subside the area overhead. A new figure of merit that comprehensively captures stability, delay, power dissipation, and area of an SRAM cell is also proposed. Based on the proposed metric, we observe that the proposed cell outperforms all, but one of the SRAM cells considered in this paper.

Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell

Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS at the nanoscale. FinFETs are double-gate devices. The two gates of a FinFET can either be shorted for higher perfomance or independently controlled for lower leakage or reduced transistor count. This gives rise to a rich design space. This chapter provides an introduction to various interesting FinFET logic design styles, novel circuit designs, and layout considerations.

https://www.springer.com/cda/content/document/cda_downloaddocument/9781441974440-c1.pdf?SGWID=0-0-45-1068439-p174029477

FinFET Circuit Design

A new seven transistors (7T) dual threshold voltage SRAM cell is proposed in this paper for simultaneously reducing the active and standby mode power consumption while enhancing the data stability and the read speed. With the new 7T SRAM cell, the storage nodes are isolated from the bitlines during a read operation, thereby enhancing the data stability as compared to the standard six transistors (6T) SRAM circuits. The transistors of the cross-coupled inverters are not on the critical read delay path with the new technique. Minimum sized dual-threshold-voltage transistors are therefore conveniently used in the cross-coupled inverters for significantly reducing the leakage power consumption without causing a degradation in the read speed. With the proposed 7T SRAM circuit, the static noise margin and the read speed are enhanced by up to 87% and 17%, respectively, as compared to the conventional 6T SRAM circuits. Furthermore, the leakage and the write power consumptions of the proposed dual-V, SRAM circuit are reduced by up to 66% and 35%, respectively, as compared to the conventional 6T SRAM circuits in a 65 nm CMOS technology.

Low power and robust 7T dual-V t SRAM circuit

Scaling of the standard single-gate bulk MOSFETs faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the leakage current and enhanced sensitivity to process variations. Multi-gate MOSFET technologies mitigate these limitations by providing a stronger control over a thin silicon body with multiple electrically coupled gates. Double-gate FinFET is the most attractive choice among the multi-gate transistor architectures because of the self-alignment of the two gates and the similarity of the fabrication steps to the existing standard CMOS technology. New latches and flip-flops based on independent-gate FinFETs are proposed in this paper to simultaneously reduce the power consumption and the circuit area. With the proposed independently biased double-gate FinFET sequential circuits, the active power consumption, the clock power, the leakage power, and the circuit area are reduced by up to 47%, 32%, 42%, and 20%, respectively, while maintaining similar speed and data stability as compared to the standard sequential circuits with tied-gate FinFETs in a 32-nm FinFET technology.

Low-Power and Compact Sequential Circuits With Independent-Gate FinFETs

Data stability of static random access memory (SRAM) circuits has become an important issue with the scaling of CMOS technology Memory arrays are also an important source of leakage since the majority of transistors are utilized for on-chip caches in today's high performance microprocessors Two six transistor SRAM cells based on independent-gate FinFET technology (IG-FinFET) are described in this paper for simultaneously reducing the active and standby mode power consumption while enhancing the data stability and the integration density With the first independent-gate FinFET SRAM cell, one gate of each double-gate access and pull-up transistor is permanently disabled in order to enhance the data stability while achieving write-ability with minimum sized transistors With the second independent-gate FinFET SRAM cell, the threshold voltages of the access transistors are dynamically adjusted during circuit operation in order to maximize the memory integration density without sacrificing the performance and stability The read stability is enhanced by up to 92% with the IG-FinFET SRAM cells as compared to a tied- gate FinFET SRAM cell with the same size transistors in a 32 nm FinFET technology Furthermore, with the IG-FinFET SRAM cells, the idle mode leakage power and the cell area are reduced by up to 36% and 11%, respectively, as compared to a standard tied-gate FinFET SRAM cell sized for comparable read stability in a 32 nm FinFET technology

Independent-gate and tied-gate FinFET SRAM Circuits: Design guidelines for reduced area and enhanced stability

Employing multiple supply voltages (multi- VDD) is an effective technique for reducing the power consumption without sacrificing speed in an integrated circuit (IC). In order to transfer signals among the circuits operating at different voltage levels specialized voltage interface circuits are required. Two novel multi-threshold voltage (multi-Vth) level converters are proposed in this paper. The new multi-Vth level converters are compared with the previously published circuits for operation at different supply voltages. When the circuits are individually optimized for minimum power consumption, the proposed level converters offer significant power savings of up to 70% as compared to the previously published circuits. Alternatively, when the circuits are individually optimized for minimum propagation delay, the speed is enhanced by up to 78% with the proposed voltage interface circuits in a 0.18- mum TSMC CMOS technology.

Low Power and High Speed Multi Threshold Voltage Interface Circuits

In the sub-65 nm CMOS technologies, subthreshold and gate dielectric leakage currents need to be simultaneously suppressed for effective energy reduction. New low-leakage circuit techniques based on multi-threshold-voltage (multi-Vt) and multi-oxide-thickness (multi-tox) standard single-gate and emerging double-gate MOSFET/FinFET technologies are presented in this paper. The leakage savings achieved with the techniques are characterized for a diverse set of logic and memory circuits that are widely used in systems-on-chips. The speed, active power, noise immunity, and area tradeoffs with the leakage reduction schemes are also evaluated.

S.A. Tawfik

Papers

Low power and robust 7T dual-V t SRAM circuit

Low-Power and Compact Sequential Circuits With Independent-Gate FinFETs

Independent-gate and tied-gate FinFET SRAM Circuits: Design guidelines for reduced area and enhanced stability

Low Power and High Speed Multi Threshold Voltage Interface Circuits

Leakage-Aware Design of Nanometer SoC