— 70°C (1 Hz) in PE (auf S. 245 wird von -20 °C bei derselben Frequenz gesprochen) als Glasübergang der amorphen Bereiche des PE anzusehen ist, der (als Maximum des tan oder G\") deutlicher hervortritt, wenn man durch physikalisch-chemische Effekte, die den Kristallisationsgrad nicht beeinflussen (z.B.: Quellung in einem unpolaren, niedermolekularen Quellungsmittel), Ànderungen des Zustands der nichtkristallinen Phasen erreichen kann. Auf diese Weise kann z.B. durch Quellung in CClj oder C„H,„ die Relaxationsstarke der nichtkristallinen Phasen verstârkt werden. Die genannten Quellungsmittel zeigen keine eigenen Dispersionsgebiete im interessierenden Bereich, sofern sie molekular dispers vorliegen [ . H. Illers, Kolloid . 190 (1963) 16, 250 (1972) 426, 231 (1967) 622J.

Density Matrix Theory and Applications

GaN provides the highest electron saturation velocity, breakdown voltage, operation temperature, and thus the highest combined frequency-power performance among commonly used semiconductors. The industrial need for compact, economical, high-resolution, and high-power terahertz (THz) imaging and spectroscopy systems are promoting the utilization of GaN for implementing the next generation of THz systems. As it is reviewed, the mentioned characteristics of GaN together with its capabilities of providing high two-dimensional election densities and large longitudinal optical phonon of ∼90  meV make it one of the most promising semiconductor materials for the future of the THz emitters, detectors, mixers, and frequency multiplicators. GaN-based devices have shown capabilities of operation in the upper THz frequency band of 5 to 12 THz with relatively high photon densities in room temperature. As a result, THz imaging and spectroscopy systems with high resolution and deep depth of penetration can be realized through utilizing GaN-based devices. A comprehensive review of the history and the state of the art of GaN-based electronic devices, including plasma heterostructure field-effect transistors, negative differential resistances, hetero-dimensional Schottky diodes, impact avalanche transit times, quantum-cascade lasers, high electron mobility transistors, Gunn diodes, and tera field-effect transistors together with their impact on the future of THz imaging and spectroscopy systems is provided.

https://www.spiedigitallibrary.org/journals/optical-engineering/volume-56/issue-9/090901/Review-of-GaN-based-devices-for-terahertz-operation/10.1117/1.OE.56.9.090901.pdf

Review of GaN-based devices for terahertz operation

Gallium nitride (GaN)-based vertical power Schottky barrier diode (SBD) has demonstrated outstanding features in high-frequency and high-power applications. This paper reviews recent progress on GaN-based vertical power SBDs, including the following sections. First, the benchmark for GaN vertical SBDs with different substrates (Si, sapphire, and GaN) are presented. Then, the latest progress in the edge terminal techniques are discussed. Finally, a typical fabrication flow of vertical GaN SBDs is also illustrated briefly.

/pdf/review-of-the-recent-progress-on-gan-based-vertical-power-26nivt99go.pdf

Review of the Recent Progress on GaN-Based Vertical Power Schottky Barrier Diodes (SBDs)

This letter reports the first demonstration of 1-kV-class AlN Schottky barrier diodes on sapphire substrates by metal organic chemical vapor deposition. The device structure mimics the silicon-on-insulator (SOI) technology, consisting of thin $n$ -AlN epilayer as the device active region and thick resistive AlN underlayer as the insulator. At room temperature, the devices show outstanding performances with a low turn-ON voltage of 1.2 V, a high ON/OFF ratio of $\sim 10^{5}$ , a low ideality factor of 5.5, and a low reverse leakage current below 1 nA. The devices also exhibit excellent thermal stability over 500 K owing to the ultra-wide bandgap of AlN. The breakdown voltage of the devices can be further improved by employing field plate, edge termination technologies, and optimizing the SOI-like device structure. This letter presents a cost-effective route to high performance AlN-based Schottky barrier diodes for high-power, high-voltage, and high-temperature applications.

Demonstration of AlN Schottky Barrier Diodes With Blocking Voltage Over 1 kV

Thermal performance characteristics of fin-shaped FETs (FinFETs) are studied and analyzed in this paper for sub-22-nm technologies using the well-calibrated TCAD simulations. In this paper, we show that bulk FinFETs have a relatively better thermal performance as compared with SOI FinFETs. In order to understand the isothermal characteristics of these devices because of thermal effects, we use pulse rise-time as well as ac conductance methods. We demonstrate that the ac conductance method fails to accurately capture thermal time constants for FinFETs, as self-heating and gate resistance regions are indistinguishable from each other. A pulse rise-time method gives isothermal characteristics of these devices. As verified from both these independent techniques, only at high frequencies (>1 GHz), FinFETs show a suppression of thermally induced degradation, which can be attributed to their higher surface-to-volume ratio. It is observed that bulk FinFETs will perform better than SOI FinFETs for small effective fin heights. However, as we show in this paper, increased body doping in bulk FinFETs will increase the self-heating effects. Channel length scaling in FinFETs, which shows a decrease in drain current degradation with heating, will be an important design parameter for sub-22-nm devices.

A Thermal-Aware Device Design Considerations for Nanoscale SOI and Bulk FinFETs

In this paper, for the first time, we propose a partial silicon-on-insulator (P-SOI) lateral double-diffused metal-oxide-semiconductor-field-effect-transistor (LDMOSFET) with a modified buried layer in order to improve breakdown voltage (BV) and self-heating effects (SHEs). The main idea of this work is to control the electric field by shaping the buried layer. With two steps introduced in the buried layer, the electric field distribution is modified. Also a P-type window introduced makes the substrate share the vertical voltage drop, leading to a high vertical BV. Moreover, four interface electric field peaks are introduced by the buried P-layer, the Si window and two steps, which modulate the electric field in the SOI layer and the substrate. Hence, a more uniform electric field is obtained; consequently, a high BV is achieved. Furthermore, the Si window creates a conduction path between the active layer and substrate and alleviates the SHE. Two-dimensional simulations show that the BV of double step partial silicon on insulator is nearly 69% higher and alleviates SHEs 17% in comparison with its single step partial SOI counterpart and nearly 265% higher and alleviate SHEs 18% in comparison with its conventional SOI counterpart.

https://iopscience.iop.org/article/10.1088/0268-1242/26/9/095005/pdf

A new partial SOI-LDMOSFET with a modified buried oxide layer for improving self-heating and breakdown voltage

A novel partial SOI LDMOSFET with periodic buried oxide for breakdown voltage and self heating effect enhancement

A novel partial SOI LDMOSFET with a trench and buried P layer for breakdown voltage improvement

In this paper, we studied the enhancement of the breakdown voltage in the 4H–SiC MESFET–MOSFET (MES–MOSFET) structure which we have proposed in our previous work. We compared this structure with Conventional Bulk-MOSFET (CB-MOSFET) and Field plated Conventional Bulk-MOSFET (FCB-MOSFET) structures. The 4H–SiC MES–MOSFET structure consists of two additional schottky buried gates which behave like a Metal on Semiconductor (MES) at the interface of the active region and substrate. The motivation for this structure was to enhance the breakdown voltage by introducing a new technique of utilizing the reduced surface field (RESURF) concept. In our comparison and investigation we used a two-dimensional device simulator. Our simulation results show that the breakdown voltage of the proposed structure is 3.7 and 2.9 times larger than CB-MOSFET and FCB-MOSFET structures, respectively. We also showed that the threshold voltage and the slope of drain current (ID) as a function of drain–source voltage (VDS) for all the structures is the same.

S. E. Jamali Mahabadi

Papers

A new partial SOI-LDMOSFET with a modified buried oxide layer for improving self-heating and breakdown voltage

A novel partial SOI LDMOSFET with periodic buried oxide for breakdown voltage and self heating effect enhancement

A novel partial SOI LDMOSFET with a trench and buried P layer for breakdown voltage improvement

Comprehensive study of a 4H–SiC MES–MOSFET

Upper drift region double step partial SOI LDMOSFET: A novel device for enhancing breakdown voltage and output characteristics