The lucky-electron concept is successfully applied to the modeling of channel hot-electron injection in n-channel MOSFET's, although the result can be interpreted in terms of electron temperature as well. This results in a relatively simple expression that can quantitatively predict channel hot-electron injection current in MOSFET's. The model is compared with measurements on a series of n-channel MOSFET's and good agreement is achieved. In the process, new values for many physical parameters such as hot-electron scattering mean-free-path, impact-ionization energy are determined. Of perhaps even greater practical significance is the quantitative correlation between the gate current and the substrate current that this model suggests.

Lucky-electron model of channel hot-electron injection in MOSFET'S

The phenomenon of and the physical mechanisms for the generation of minority carriers in the substrate of NMOS and CMOS are studied Secondary impact ionization is not responsible The responsible mechanisms are hot-electron-induced photocarrier generation and, under extreme conditions, forward biasing of the source-substrate junction The photon generation is believed to be due to the bremsstrahlung of the channel hot electrons A theoretical model based on the lucky electron concept and the bremsstrahlung mechanism is proposed The calculated characteristics of photon generation agree well with experimental results About 2 × 10-5photogenerated minority carriers are generated for every (primary) impact-ionization event in NMOSFET Photocarrier-induced leakage current can be fitted with either an inverse square dependence on distance or an exponential dependence with an effective decay length of about 780 µm

Hot-electron-induced photon and photocarrier generation in Silicon MOSFET's

An overview of semiconductor device modelling is presented which describes the principal methods of representing and analysing modern solid-state devices. The review deals with classical, semiclassical, particle and quantum transport methodologies and compares the relative merits of each approach. The background behind each modelling technique is briefly summarised and recent developments in each area are described. The importance of accounting for non-stationary and quantum effects in small geometry devices is emphasised.

https://iopscience.iop.org/article/10.1088/0034-4885/48/2/002/pdf

Semiconductor Device Modelling

Single-ended, robust 8T SRAM cell for low-voltage operation

In recent publications the drain-induced barrier-lowering (DIBL) effect has been included in the determination of the drain current of short-channel MOSFET's by way of analytical expressions The validity of these published expressions has not been verified so far for small-geometry devices of different parameters Further, the relationship between the threshold voltage shift and the barrier lowering due to the DIBL effect has not been clarified in the literature In our present paper we carried a detailed study of the drain-induced barrier lowering in ion-implanted 1-µm VLSI MOSFET devices, leading to a better understanding and clarification of the fundamental mechanisms involved in the DIBL variation and its effect on the threshold voltage and subthreshold current Further, we found that the calculated DIBL parameters of the analytical model reported in the literature do not agree with the numerically computed values Hence we determined a set of new geometry parameters η and B/A for the DIBL threshold relationship that can be used with the analytical model Our work stresses the necessity of the use of two-dimensional numerical simulations when accurate evaluation of the DIBL effect in short-channel MOSFET's is required Also, our results should be useful for calibrating existing analytical MOSFET models In addition, our data and method could be used as a design tool for performance optimization of micrometer and submicrometer devices

Drain-induced barrier-lowering analysis in VSLI MOSFET devices using two-dimensional numerical simulations

With the advent of 2- and 1-µm VLSI silicon technologies, evaluation of the threshold, density, power, speed, circuit margins, punchthrough, and breakdown requires three-dimensional simulations. This paper describes a computer simulation program based on a three-dimensional model for small-geometry MOSFET's. The effect of Si-SiO 2 interface charge, ion implantation in the channel, p+isolation field ion implant (channel isolations), and shape of the field oxide are all included in the model. Our three-dimensional simulations revealed a new insight into VLSI MOSFET devices. Some of these results include "wedge-like" effective channel width, the effective channel width under certain bias conditions decreases to 63 percent of its nominal value. Saddle point related to punchthrough current locus; the punchthrough current per unit width as a function of the channel width was found for the first time to decrease rapidly as the channel width was reduced below 5 µm. A decrease of punchthrough current by three orders of magnitude was observed as the channel width was reduced from 2 to 1 µm. The breakdown voltage of small-geometry devices increases as the channel width decreases. Subthreshold current, potential and electric field distributions, and threshold voltage are significantly different from those calculated using two-dimensional analysis. This simulation program can be used for design of small-geometry MOSFET's and estimation of small-geometry effects in submicrometer size devices. It can be used to evaluate new VLSI and VHSIC technologies. Finally it can be used to test simple models for use with CAD programs.

Three-dimensional simulation of VLSI MOSFET's: The three-dimensional simulation program WATMOS

With the advent of 2- and 1-/spl mu/m VLSI silicon technologies, evaluation of the threshold, density, power, speed, circuit margins, punchthrough, and breakdown requires three-dimensional simulations. This paper describes a computer simulation program based on a three-dimensional model for small-geometry MOSFET's. The effect of Si-SiO/sub 2/ interface charge, ion implantation in the channel, p/sup +/ isolation field ion implant (channel isolations), and shape of the field oxide are all included in the model. Our three-dimensional simulations revealed a new insight into VLSI MOSFET devices. Some of these results include "wedge-like" effective channel width, the effective channel width under certain bias conditions decreases to 63 percent of its nominal value. Saddle point related to punchthrough current locus; the punchthrough current per unit width as a function of the channel width was found for the first time to decrease rapidly as the channel width was reduced below 5 /spl mu/m. A decrease of punchthrough current by three orders of magnitude was observed as the channel width was reduced from 2 to 1 /spl mu/m. The break-down voltage of small-geometry devices increases as the channel width decreases. Subthreshold current, potential and electric field distributions, and threshold voltage are significantly different from those calculated using two-dimensional analysis. This simulation program can be used for design of small-geometry MOSFET's and estimation of small-geometry effects in submicrometer size devices, It can be used to evaluate new VLSI and VHSIC technologies. Finally it can be used to test simple models for use with CAD programs.

S.G. Chamberlain

Papers

Three-dimensional simulation of VLSI MOSFET's: The three-dimensional simulation program WATMOS

Three-Dimensional Simulation of VLSI MOSFET's: The Three-Dimensional Simulation Program WATMOS