In this paper, the intermodulation distortion (IMD) behavior of LDMOS transistors is treated. First, an analysis is performed to explain measured IMD characteristics in different classes of operation. It is shown that the turn-on region plays an important role in explaining measured IMD behavior, which may also give a clue to the excellent linearity of LDMOS transistors. Thereafter, with this knowledge, a new empirical large-signal model with improved capability of predicting IMD in LDMOS amplifiers is presented. The model is verified against various measurements at low as well as high frequency in a class-AB power amplifier circuit.

/pdf/prediction-of-imd-in-ldmos-transistor-amplifiers-using-a-new-2wzfrozcuy.pdf

Prediction of IMD in LDMOS transistor amplifiers using a new large-signal model

The authors demonstrate that silicon-on-insulator (SOI) MESFETs can be fabricated alongside SOI CMOS with no changes to the foundry process flow. The MESFETs operate in depletion mode with a threshold voltage of -0.6 V for a gate length of 0.6 mum. The breakdown voltage of the MESFETs greatly exceeds that of the CMOS devices and varies in the range of 12-58 V depending upon the channel access length, i.e., the distance from the edge of the gate to the edge of the drain region. For MESFETs with a gate length of 0.6 mum and an access length of 0.6 mum, the peak cutoff frequency exceeds 7 GHz. The maximum available gain increases with drain bias and values of fmax range from 17 GHz at VDD = 2 V to 22 GHz at VDD = 8 V

CMOS-Compatible SOI MESFETs With High Breakdown Voltage

The present work considers electrothermal simulation of LDMOS devices and associated nonequilibrium effects. Simulations have been performed on three kinds of LDMOS: bulk Si, partial SOI and full SOI. Differences between equilibrium and nonequilibrium modeling approaches are examined. The extent and significance of thermal nonequilibrium is determined from phonon temperature distributions obtained using a common electronic solution and three different heating models (Joule heating, electron/lattice scattering, phonon scattering). The results indicate that, under similar operating conditions, nonequilibrium behavior is more significant in the case of full SOI devices, where the extent of nonequilibrium is estimated to be twice that of the partial SOI device and four times that of the bulk device. Time development of acoustic phonon and lattice temperatures in the electrically active region indicates that nonequilibrium effects are significant for times less than 10 ns.

http://tplab.vuse.vanderbilt.edu/docs/raman03-SSE.pdf

Simulation of nonequilibrium thermal effects in power LDMOS transistors

We propose a new empirical large-signal model of silicon laterally diffused MOSFETs for the design of various modes of high-power amplifiers. The new channel current model has only nine parameters that represent the unique operation principles of a MOSFET. In the channel current model, we include the thermal phenomena of high-power devices. To accurately characterize high-power devices, we incorporate the channel heating and heat-sink heating effects by providing two thermal capacitances and two thermal resistances. Nonlinear capacitances, including deep subthreshold and triode regions, as well as normal saturation regions, are extracted and modeled. For validation of our model, a 1.4-GHz 5-W amplifier is implemented, and the measured and simulated results match very well.

A new empirical large-signal model of Si LDMOSFETs for high-power amplifier design

This paper describes how device simulation may be used for the modeling, analysis, and design of radio-frequency (RF) laterally diffused metal-oxide-semiconductor (LDMOS) transistors. Improvements to device analysis needed to meet the requirements of RF devices are discussed. Key modeling regions of the LDMOS device are explored and important physical effects are characterized. The LDMOS model is compared to dc and small-signal ac measurements for calibration purposes. Using the calibrated model, large-signal accuracy is verified using harmonic distortion simulation, and intermodulation analysis. Predictive analysis and a study of the structure's parasitic components are also presented. Load-pull simulation is used to analyze matching network effects to determine the best choices for device impedance matching.

Modeling, analysis, and design of RF LDMOS devices using harmonic-balance device simulation

This paper describes the design and optimization of an 80 V silicon RF LDMOSFET used in a power amplifier for base station applications. The transistor was prototyped using the doping profiles extracted from an experimental device and extensive two-dimensional (2-D) simulations were performed to characterize the DC and RF performance of the device. A good match between the measured and simulated data is reported. A simple circuit model was developed which accurately predicts the DC and RF characteristics in circuit simulators. It is shown through 2-D simulations that the LDD region in the LDMOSFET can be modeled as a JFET. A methodology for the accurate extraction of model parameters for the circuit model is discussed. It is shown that the DC and RF performances of the circuit model closely match the measured data. Advanced mixed device and circuit simulations were used to obtain S-parameters of the device which provide new insights into device physics and also the basis for statistical process control studies.

Modeling and characterization of an 80 V silicon LDMOSFET for emerging RFIC applications

This paper presents a systematic study of the limitations imposed by thermal and packaging considerations on radio-frequency (RF) performance of Si bulk and silicon-on-insulator (SOI) lateral DMOSFET's (LDMOSFET's). Several bulk and SOI devices are studied with the help of measurements as well as two-dimensional device simulations incorporating electrothermal models. Model parameters are extracted and used in circuit simulators to perform RF characterization of these devices. Further, a new three-region theory for the LDMOSFET is discussed and used to evaluate the static and RF performance of the devices in a nonisothermal environment. This paper shows that the package plays an important role in RF performance of SOI and bulk devices due to self-heating effects within the device. A detailed DC and RF performance evaluation is presented. Significant drift is observed in RF performance of bulk and SOI devices due to self-heating considerations. The physical understanding of these thermal effects within the device can facilitate the design of better packages for bulk and SOI devices.

Thermal and package performance limitations in LDMOSFET's for RFIC applications

This paper presents the design and optimization of a 80 V LDMOSFET used in RF power amplifiers for cellular base station applications. SRP data from an experimental device was used to prototype the device using advanced 2-D process and device simulators. DC and RF characterization has been performed for the device. A proper match has been obtained between the measured and simulated data. A simple circuit model has been developed in which each of the components has been associated with the physical principles of device operation. A close match between the measured and modeled RF data has been reported.

Modeling and characterization of 80 V LDMOSFET for RF communications

This paper presents the design optimization of LDMOSFET structures for use as power amplifiers in mobile wireless applications. A detailed study has been carried out to evaluate the influence of the device substrate on the RF performance. The performance of devices with bulk and Silicon-on-insulator (SOI) substrates has been compared for 50 V LDMOSFETs. In both cases, p-type and n-type epitaxial layers were considered. Extensive two-dimensional simulations have been performed to understand the device dynamics and to optimize the devices for better RF performance. A simple physics-based circuit model has been developed to enable large signal simulations for RF characterization. It is shown that bulk devices on n-type epitaxial layers yield the highest output RF power for a given voltage and current rating. SOI devices offer comparable RF performance with less area for a given rating, but suffer from self-heating effects. Thick-film SOI is shown as a viable power amplifier technology for integrated RFIC applications.

Design and modeling of bulk and SOI power LDMOSFETs for RF wireless applications

This paper presents the evaluation of performance of 50 V LDMOSFETS designed in bulk Si and SOI for use in power amplifiers for cellular base stations. SOI technology has been fast emerging as the major technology for RF applications due to its inherent advantages such as lower parasitics, lower on-resistance and better noise immunity. Extensive 2-D simulations on an advanced process and device simulator have been performed to study the carrier dynamics in the LDMOSFET. This allows for a better understanding of the means to reduce the device parasitics, that are a major factor limiting the RF performance of the transistor. A simple circuit model has been developed for the LDMOSFET for use in performing large signal AC analyses for RF characterization. Non-Isothermal simulations on the SOI device have shown that at the feature dimensions under consideration, the self heating does not affect the DC and RF performance significantly.

S. K. Leong

Papers

Modeling and characterization of an 80 V silicon LDMOSFET for emerging RFIC applications

Thermal and package performance limitations in LDMOSFET's for RFIC applications

Modeling and characterization of 80 V LDMOSFET for RF communications

Design and modeling of bulk and SOI power LDMOSFETs for RF wireless applications

Performance evaluation of bulk Si and SOI RF LDMOSFETs for emerging RFIC applications