S
S. Maheshwaram
Researcher at Indian Institute of Technology Roorkee
Publications - 34
Citations - 289
S. Maheshwaram is an academic researcher from Indian Institute of Technology Roorkee. The author has contributed to research in topics: CMOS & Logic gate. The author has an hindex of 8, co-authored 28 publications receiving 197 citations. Previous affiliations of S. Maheshwaram include National Institute of Technology, Warangal.
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Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS
TL;DR: In this article, a novel vertical silicon nanowire-based (NW) complementary metal-oxide-semiconductor (CMOS) technology for logic applications is investigated and the performance and the behavior of two-and single-wire CMOS inverters are simulated and analyzed.
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Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis
TL;DR: In this paper, the analytical models of parasitic resistance and capacitance of vertical nanowire (VNW) FETs were presented, considering device structural asymmetry, and the effect of channel, source-drain extension lengths, and nanowires diameter on device and VNW CMOS performance for 15 nm node.
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A Degradation Model of Double Gate and Gate-All-Around MOSFETs With Interface Trapped Charges Including Effects of Channel Mobile Charge Carriers
TL;DR: In this paper, an analytic degradation model of double-gate (DG) and gate-all-around (GAA) MOS field effect transistors (MOSFETs) in the presence of localized interface charge is presented.
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Radiation Effects in Si-NW GAA FET and CMOS Inverter: A TCAD Simulation Study
Gaurav Kaushal,Surendra S. Rathod,S. Maheshwaram,Sanjeev Kumar Manhas,A. K. Saxena,Sudeb Dasgupta +5 more
TL;DR: In this article, the response of silicon-nanowire (Si-NW) gate-all-around (GAA) field effect transistor to total ionizing dose (TID) effects and assessed the impact of single-event effects (SEEs) in simple inverter circuit built from such devices.
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Effect of Load Capacitance and Input Transition Time on FinFET Inverter Capacitances
Archana Pandey,Swati Raycha,S. Maheshwaram,Sanjeev Kumar Manhas,Sudeb Dasgupta,A. K. Saxena,Bulusu Anand +6 more
TL;DR: In this article, a new extension transistor-induced capacitance shielding (ETICS) phenomenon is reported, where the FinFET extension region forms a transistor, which shields gate-extension fringing field capacitance.