In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifier's most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.

Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization

Using state-variable flow graphs and simple operational configurations suitable for integration, a theory for insensitive transfer function realization in terms of integrated circuits is discussed. The theory emphasizes the decomposition into second-order systems that are developed, following state-space concepts, with special reference to their sensitivity which is shown to be very low for high operational amplifier gains.

State-Variable Synthesis for Insensitive Integrated Circuit Transfer Functions

Circuit design techniques are described for switched-capacitor filters, modulators, rectifiers, detectors, and oscillators. The applications of these circuits in telecommunications, speech processing, and other signal-processing systems are also briefly discussed.

Switched-capacitor circuit design

Charge-coupled devices (CCDs) have been fabricated on high-resistivity, n-type silicon. The resistivity, on the order of 10 000 /spl Omega//spl middot/cm, allows for depletion depths of several hundred micrometers. Fully depleted, back-illuminated operation is achieved by the application of a bias voltage to an ohmic contact on the wafer back side consisting of a thin in situ doped polycrystalline silicon layer capped by indium tin oxide and silicon dioxide. This thin contact allows for a good short-wavelength response, while the relatively large depleted thickness results in a good near-infrared response.

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Fully depleted, back-illuminated charge-coupled devices fabricated on high-resistivity silicon

A capacitor error-averaging technique is applied to perform an accurate multiply-by-two (*2) function required in high-resolution pipelined analog-to-digital (A/D) converters. Errors resulting from capacitor mismatch and switch feedthrough are corrected in the analog domain without using digital calibration and/or trimming. A differential pipelined A/D converter that achieves a throughput rate of 1 Msample/s with 12 bits of linearity has been made and evaluated. A prototype pipelined A/D converter implemented using a double-poly 1.75- mu m CMOS process consumes 400 mW with a 5-V single supply and occupies 14 mm/sup 2/, including all digital logic and output buffers. >

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A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter

The authors discuss the noise measured at the output of a buried channel charge-coupled device (BCCD) linear shift register. The measured noise arises from four sources; the electrical insertion of signal charge, the output amplifier, dark current, and bulk state trapping. In making these measurements the concept of correlated double sampling was used in an output circuit which had a noise level which was equivalent to less than 30 noise electrons.

Noise in buried channel charge-coupled devices

In this paper we discuss the noise measured at the output of a buried channel charge-coupled device (BCCD) linear shift register. The measured noise arises from four sources; the electrical insertion of signal charge, the output amplifier, dark current, and bulk state trapping. In making these measurements the concept of correlated double sampling was used in an output circuit which had a noise level which was equivalent to less than 3O noise electrons. A critical component in this output was a low noise MOSFET which was achieved by use of the buried channel technology. A low noise input structure for electrical insertion of signal charge was used which introduced a signal which had a noise level which ranged from less than 10 e-to as high as 60 e-depending on the size of the signal charge. The dark current noise was found to be well characterized as a shot noise and levels on the order of 20 e-were measured. The above low noise levels made possible direct measurement of the noise due to bulk state trapping, and depending on the signal size and clock rate noise levels were measured which ranged from less than 10 to over 100 noise electrons. One of the most important bulk traps was found to be due to gold impurities which had a density of ∼ 2 × 1011cm-3.

This paper describes a new approach to the fabrication of a variety of monolithic direct coupled amplifiers with typical equivalent differential input drifts of 0.1 to 0.2 /spl mu/v//spl deg/C. These amplifiers exhibit a significant improvement in temperature stability over current state-of-the-art IC amplifiers, and complete with chopper stabilized units in many respects. In these amplifiers, a monolithic silicon wafer is maintained at a near constant temperature by means of an electrically separate temperature-control circuit diffused within the same substrate. A thermal-electrical analogy is used to predict temperature gradients on the surface of the silicon bar. Performance of several amplfier circuit configurations is discussed.

S.P. Emmons

Papers

Noise in buried channel charge-coupled devices

Noise in buried channel charge-coupled devices

Very low drift complementary semiconductor network DC amplifiers